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user?s manual pd789425 pd789445 pd789426 pd789446 pd789435 pd789455 pd789436 pd789456 pd78f9436 pd78f9456 pd789426, 789436, 789446, 789456 subseries 8-bit single-chip microcontrollers printed in japan document no. u15075ej2v1ud00 (2nd edition) date published august 2005 n cp(k) ?
2 user?s manual u15075ej2v1ud [memo]
user?s manual u15075ej2v1ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
4 user?s manual u15075ej2v1ud fip and eeprom are trademarks of nec electronics corporation. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trad emarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc.
user?s manual u15075ej2v1ud 5 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of august, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incor porate sufficient safet y measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
6 user?s manual u15075ej2v1ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j05.6 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-265 40 10 ? tyskland filial taeby, sweden tel: 08-63 87 200 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
user?s manual u15075ej2v1ud 7 [memo]
8 user?s manual u15075ej2v1ud introduction target readers this manual is intended to give user engineers an understanding of the functions of the pd789426, 789436, 789446, and 789456 subserie s to design and develop its application systems and programs. target products: ? pd789426 subseries: pd789425, 789426 ? pd789436 subseries: pd789435, 789436 ? pd789446 subseries: pd789445, 789446 ? pd789456 subseries: pd789455, 789456 purpose this manual is designed to deepen your understanding of the following functions using the following organization. organization two manuals are available for the pd789426, 789436, 789446, and 789456 subseries: this manual and the instruction manual (common to the 78k/0s series). pd789426, 789436, 789446, and 789456 subseries user?s manual 78k/0s series user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other internal peripheral functions ? electrical specifications ? cpu function ? instruction set ? instruction description how to use this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to understand the overa ll functions of the pd789426, 789436, 789446, and 789456 subseries read this manual in the order of the contents . ? how to read register formats the name of a bit whose number is enclo sed in brackets is reserved for the assembler and is defined for the c compiler by the header file sfrbit.h. ? to learn the detailed functions of a register whose register name is known see appendix c register index . ? to learn the details of the instru ction functions of the 78k/0s series refer to 78k/0s series instructions user?s manual (u11047e) separately available. ? to learn the electrical specifications of the pd789426, 789436, 789446, and 789456 subseries see chapter 20 electrical specifications . ? the oscillation frequency of the ma in system clock is regarded as f x for crystal/ceramic oscillation, and f cc for rc oscillation. the value for crystal/ceramic oscillation (f x ) is typically described unless otherwise specified.
user?s manual u15075ej2v1ud 9 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd789426, 789436, 789446, 789456 subseries user?s manual this manual 78k/0s series instructions user?s manual u11047e documents related to developmen t software tools (user?s manuals) document name document no. operation u14876e language u14877e ra78k0s assembler package structured assembly language u11623e operation u14871e cc78k0s c compiler language u14872e operation (windows tm based) u15373e sm78k series system simulator ver. 2.30 or later external part user open in terface specification u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e project manager ver. 3.12 or later (windows based) u14610e documents related to development hardware tools (user?s manuals) document name document no. ie-78k0s-ns in-circuit emulator u13549e ie-78k0s-ns-a in-circuit emulator u15207e ie-789456-ns-em1 emulation board u16289e caution the related documen ts listed above are subject to change without notice. be sure to use the latest version of each document for designing.
10 user?s manual u15075ej2v1ud documents related to flash memory writing document name document no. pg-fp3 flash memory progr ammer user's manual u13502e pg-fp4 flash memory progr ammer user's manual u15260e other related documents document name document no. semiconductor selection guide -products and packages- x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? website (http:// www.necel.com/pkg/en/m ount/index.html). caution the related documen ts listed above are subject to change without notice. be sure to use the latest version of each document for designing.
user?s manual u15075ej2v1ud 11 contents chapter 1 general ........................................................................................................... ............... 25 1.1 features ................................................................................................................. ..................... 25 1.2 applications ............................................................................................................. .................. 25 1.3 ordering information ..................................................................................................... ............ 26 1.4 pin configuration (top view) .................................. ........................................................... ...... 27 1.4.1 pin configuration of pd789426, 789436 subserie s (top vi ew) ................................................... 27 1.4.2 pin configuration of pd789446, 789456 subserie s (top vi ew) ................................................... 28 1.5 78k/0s series lineup ..................................................................................................... ........... 30 1.6 block diagram............................................................................................................ ................ 33 1.6.1 block diagram of pd789426, 789436 subs eries ......................................................................... 33 1.6.2 block diagram of pd789446, 789456 subs eries ......................................................................... 34 1.7 overview of functions .................................................................................................... .......... 35 chapter 2 pin funct ions.................................................................................................... ........... 37 2.1 list of pin functions .................................................................................................... ............. 37 2.2 description of pin functions ................................... .......................................................... ....... 40 2.2.1 p00 to p03 (p ort 0) .................................................................................................... ................... 40 2.2.2 p10, p11 (por t 1) ...................................................................................................... .................... 40 2.2.3 p20 to p26 (p ort 2) .................................................................................................... ................... 40 2.2.4 p30 to p33 (p ort 3) .................................................................................................... ................... 41 2.2.5 p50 to p53 (por t 5) ..................................................................................................... .................. 41 2.2.6 p60 to p65 (p ort 6) .................................................................................................... ................... 41 2.2.7 p70 to p72 (p ort 7) .................................................................................................... ................... 42 2.2.8 p80, p81 (por t 8) ...................................................................................................... .................... 42 2.2.9 p90 to p97 (p ort 9) .................................................................................................... ................... 42 2.2.10 s0 to s14 ............................................................................................................. ......................... 42 2.2.11 com0 to com3 .......................................................................................................... .................. 42 2.2.12 v lc0 to v lc2 ............................................................................................................................... .... 42 2.2.13 c aph, c apl............................................................................................................ ..................... 42 2.2.14 reset ................................................................................................................. ......................... 42 2.2.15 x1, x2 ................................................................................................................ ........................... 42 2.2.16 cl1, cl2 (in case of rc oscillation (ma sk option) only) ............................................................... 42 2.2.17 xt 1, xt2.............................................................................................................. ......................... 43 2.2.18 v dd ............................................................................................................................... ................. 43 2.2.19 v ss ............................................................................................................................... ................. 43 2.2.20 v pp ( pd78f9436, 78f 9456 only) ................................................................................................ 43 2.2.21 ic (mask rom versi on onl y) ............................................................................................ ............. 43 2.3 pin input/output circuits and recommended c onnection of unused pins ....................... 44
12 user?s manual u15075ej2v1ud chapter 3 cpu archi tecture ................................................................................................. .....46 3.1 memory space............................................................................................................. ...............46 3.1.1 internal progr am memory space ........................................................................................... ........ 52 3.1.2 internal data memory (internal high-s peed ram) s pace ............................................................... 53 3.1.3 special functi on register (sfr) area ................................................................................... .......... 53 3.1.4 data me mory addr essing ................................................................................................. ............. 54 3.2 processor registers ...................................................................................................... ............60 3.2.1 contro l regist ers...................................................................................................... ...................... 60 3.2.2 general- purpose regi sters.............................................................................................. ............... 63 3.2.3 special func tion register s (sfrs)...................................................................................... ............ 64 3.3 instruction address addressing .................................. ......................................................... ...67 3.3.1 relati ve addre ssing.................................................................................................... ................... 67 3.3.2 immedi ate addre ssing ................................................................................................... ................ 68 3.3.3 table i ndirect addr essing .............................................................................................. ................ 69 3.3.4 regist er addre ssing .................................................................................................... .................. 69 3.4 operand address addressing ............................................................................................... ...70 3.4.1 direc t addre ssing ...................................................................................................... .................... 70 3.4.2 short di rect addr essing ................................................................................................ ................. 71 3.4.3 special function register (sfr ) addre ssing ............................................................................. ...... 72 3.4.4 regist er addre ssing .................................................................................................... .................. 73 3.4.5 register indirect addressi ng........................................................................................... ............... 74 3.4.6 bas ed addre ssing ....................................................................................................... .................. 75 3.4.7 sta ck addre ssing ....................................................................................................... .................... 75 chapter 4 port functio ns ................................................................................................... ........76 4.1 port functions........................................................................................................... .................76 4.2 port configuration ....................................................................................................... ..............79 4.2.1 port 0 ................................................................................................................. ........................... 80 4.2.2 port 1 ................................................................................................................. ........................... 81 4.2.3 port 2 ................................................................................................................. ........................... 82 4.2.4 port 3 ................................................................................................................. ........................... 88 4.2.5 port 5 ................................................................................................................. ........................... 90 4.2.6 port 6 ................................................................................................................. ........................... 91 4.2.7 port 7 ................................................................................................................. ........................... 92 4.2.8 port 8 ( pd789426, 789436 subser ies onl y) ................................................................................ 93 4.2.9 port 9 ( pd789426, 789436 subser ies onl y) ................................................................................ 94 4.3 registers controlling port function ...................................................................................... ..95 4.4 port function operation.................................................................................................. ........101 4.4.1 writi ng to i/o port .................................................................................................... .................... 101 4.4.2 reading from i/o port.................................................................................................. ................ 101 4.4.3 arithmetic operation of i/o port ....................................................................................... ............ 101 chapter 5 clock generator .................................................................................................. ..102 5.1 clock generator functions................................................................................................ .....102
user?s manual u15075ej2v1ud 13 5.2 clock generator configuration ............................... ............................................................. .. 102 5.3 registers controlling clock generator .................. ............................................................... 104 5.4 system clock oscillators................................................................................................. ....... 108 5.4.1 main system clock oscillato r (crystal/ceramic oscilla tion)............................................................ 1 08 5.4.2 main system clock oscilla tor (rc oscillation) (mask opt ion) ........................................................ 109 5.4.3 subsystem clock osc illator ............................................................................................. ............. 109 5.4.4 example of inco rrect resonator connec tion .............................................................................. ... 110 5.4.5 divi der circ uit ........................................................................................................ ...................... 114 5.4.6 when no subsyst em clock is used ........................................................................................ ...... 114 5.5 clock generator operation...................................... .......................................................... ..... 115 5.6 changing setting of system clock and cpu clock . ............................................................ 116 5.6.1 time required for switchi ng between system clo ck and cpu cl ock............................................. 116 5.6.2 switching between syst em clock and cp u cloc k ........................................................................ 117 chapter 6 16-bit timer 90 ................................................................................................. ........... 119 6.1 16-bit timer 90 functions ........................................ ........................................................ ....... 119 6.2 16-bit timer 90 configuration ................................. ........................................................... .... 120 6.3 registers controlling 16-bit timer 90 ..................... .............................................................. 1 23 6.4 16-bit timer 90 operation ..................................... ........................................................... ....... 127 6.4.1 operation as timer interr upt ........................................................................................... ............. 127 6.4.2 operati on as time r out put.............................................................................................. .............. 129 6.4.3 capt ure operat ion ...................................................................................................... ................. 130 6.4.4 16-bit time r counter 90 r eadout ........................................................................................ ........... 131 6.4.5 buzzer output oper ation ................................................................................................ ............. 132 6.5 notes on 16-bit timer 90................................................................................................. ........ 133 6.5.1 notes on us ing 16-bit timer 90 ......................................................................................... ........... 133 6.5.2 restrictions on rewrit ing 16-bit compar e regist er 90 ................................................................... 135 chapter 7 8-bit timers 50, 60 ............................................................................................ ........ 137 7.1 8-bit timers 50, 60 functions.................................. .......................................................... ..... 137 7.2 8-bit timers 50, 60 configuration ........................... ............................................................. .. 138 7.3 registers controlling 8-bit timers 50, 60 ........... .................................................................. 144 7.4 8-bit timers 50, 60 operation ............................... ............................................................. ..... 150 7.4.1 operation as 8-bit time r count er....................................................................................... ........... 150 7.4.2 operation as 16-bit time r count er...................................................................................... .......... 158 7.4.3 operation as carrier generat or ......................................................................................... ........... 165 7.4.4 pwm free-running mode operation (tim er 50) ............................................................................. 17 0 7.4.5 operation as pwm output (t imer 60) ..................................................................................... ..... 174 7.5 notes on using 8-bit timers 50, 60......................... .............................................................. .176 chapter 8 watch timer ...................................................................................................... ......... 177 8.1 watch timer functions .................................................................................................... ....... 177 8.2 watch timer configuration...................................... .......................................................... ..... 178 8.3 watch timer control register ............................................................................................. ... 179 8.4 watch timer operation .................................................................................................... ....... 180
14 user?s manual u15075ej2v1ud 8.4.1 operation as watch timer ............................................................................................... ............. 180 8.4.2 operation as interval timer ............................................................................................ .............. 180 chapter 9 watchdog timer ................................................................................................... ....182 9.1 watchdog timer functions................................................................................................. ....182 9.2 watchdog timer configuration ............................................................................................. .183 9.3 watchdog timer control regist ers........................................................................................1 84 9.4 watchdog timer operation................................................................................................. ....186 9.4.1 operation as watchdog timer ............................................................................................ .......... 186 9.4.2 operation as interval timer ............................................................................................ .............. 187 chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) .......................188 10.1 8-bit a/d converter func tions........................................................................................... .....188 10.2 8-bit a/d converter configuration ........................ ............................................................... ..188 10.3 8-bit a/d converter control registers .................... ..............................................................1 91 10.4 8-bit a/d converter oper ation........................................................................................... .....193 10.4.1 basic operation of 8-bit a/d conver ter................................................................................ ......... 193 10.4.2 input voltage and conversi on resu lt................................................................................... ......... 194 10.4.3 operation mode of 8-bit a/d conver ter................................................................................. ....... 196 10.5 cautions related to 8-bit a/d converter.............. .................................................................19 7 chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) .....................201 11.1 10-bit a/d converter functions................................ .......................................................... ....201 11.2 10-bit a/d converter configuration ......................... ............................................................. .201 11.3 10-bit a/d converter control registers .................. ..............................................................20 4 11.4 10-bit a/d converter operation............................. ............................................................. ....206 11.4.1 basic operation of 10-bit a/d conver ter............................................................................... ........ 206 11.4.2 input voltage and conversi on resu lt................................................................................... .......... 207 11.4.3 operation mode of 10-bit a/d conver ter................................................................................ ...... 209 11.5 cautions related to 10-bit a/d converter............ .................................................................210 chapter 12 serial interface 20 ................................ ............................................................ ..214 12.1 serial interface 20 functions ........................................................................................... .......214 12.2 serial interface 20 configuration................... .................................................................... .....214 12.3 serial interface 20 control registers .................... ............................................................... ..218 12.4 serial interface 20 oper ation ........................................................................................... .......225 12.4.1 operat ion stop mode................................................................................................... ................ 225 12.4.2 asynchronous serial interface (u art) mode ............................................................................. . 227 12.4.3 3-wire serial i/o mode ................................................................................................ ................. 240 chapter 13 lcd controller/driver............................... ........................................................251 13.1 lcd controller/driver functions.............................. ........................................................... ...251 13.2 lcd controller/driver configuration .................... ................................................................. 251 13.3 registers controlling lcd controller/driver .......... ..............................................................253
user?s manual u15075ej2v1ud 15 13.4 setting lcd controller/driver........................................................................................... ...... 257 13.5 lcd display data memory ................................................................................................. ..... 257 13.6 common and segment signals .............................................................................................. 258 13.7 display modes........................................................................................................... ............... 260 13.7.1 three-time sl ot display example ....................................................................................... .......... 260 13.7.2 four-time sl ot display example ........................................................................................ ........... 263 13.8 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 ............................................................. 266 chapter 14 interrupt functions ................................... ......................................................... 2 67 14.1 interrupt function types................................................................................................ ......... 267 14.2 interrupt sources and configur ation..................................................................................... 267 14.3 registers controlling interrupt function ............... ............................................................... 27 0 14.4 interrupt servicing operat ion........................................................................................... ...... 276 14.4.1 non-maskable interrupt request acknowledgm ent operat ion ...................................................... 276 14.4.2 maskable interrupt r equest acknowledgment operatio n .............................................................. 278 14.4.3 multiple in terrupt se rvicing .......................................................................................... ................ 279 14.4.4 putting interr upt requests on hol d .................................................................................... ........... 281 chapter 15 standby function...................................... .......................................................... .. 282 15.1 standby function and configurat ion .................................................................................... 28 2 15.1.1 standby func tion ...................................................................................................... ................... 282 15.1.2 register cont rolling standby functi on ................................................................................. ......... 283 15.2 standby function operation .................................... .......................................................... .... 284 15.2.1 ha lt m ode............................................................................................................. .................... 284 15.2.2 st op m ode ............................................................................................................. ................... 287 chapter 16 reset function .................................................................................................. ..... 290 chapter 17 pd78f9436, 78f9456 .................................................................................................. 294 17.1 flash memory characteristics................................. ........................................................... .... 295 17.1.1 progra mming envir onment............................................................................................... ........... 295 17.1.2 comm unication mode ................................................................................................... .............. 296 17.1.3 on-boar d pin c onnecti ons .............................................................................................. ............. 299 17.1.4 connection of adapt er for flas h writ ing............................................................................... ......... 302 chapter 18 mask options .................................................................................................... ....... 304 chapter 19 instruction set ........................................ ......................................................... ..... 305 19.1 operation ............................................................................................................... ................... 305 19.1.1 operand identifie rs and descrip tion me thods ........................................................................... ... 305 19.1.2 description of ?operation? column..................................................................................... .......... 306 19.1.3 description of ?flag? column .......................................................................................... ............. 306 19.2 operation list.......................................................................................................... ................. 307
16 user?s manual u15075ej2v1ud 19.3 instructions listed by a ddressing type ...............................................................................312 chapter 20 electrical specifications....................... ..........................................................315 chapter 21 characteristics curves of lcd controller/driver (refrence values)..................................................................................................333 chapter 22 package drawings ................................................................................................ 335 chapter 23 recommended soldering conditions... ........................................................337 appendix a development tools............................................................................................... 340 a.1 software package ......................................................................................................... ...........342 a.2 language processing software ................................... .......................................................... 342 a.3 control software .......................................................................................................... ............343 a.4 flash memory writing tools ............................................................................................... ....343 a.5 debugging tools (hardware)............................................................................................... ...344 a.6 debugging tools (software) ............................................................................................... ....345 appendix b notes on target system design .......................................................................346 appendix c register index .................................................................................................. .......350 c.1 register index (alphabetic order of register name)...........................................................350 c.2 register index (alphabetic order of register symbol) .......................................................352 appendix d revision history ................................................................................................ .....354
user?s manual u15075ej2v1ud 17 list of figures (1/6) figure no. title page 2-1 pin input/ou tput cir cuits................................................................................................. .................................45 3-1 memory map ( pd789425, 789435) .............................................................................................................. .46 3-2 memory map ( pd789426, 789436) .............................................................................................................. .47 3-3 memory map ( pd78f 9436) ..................................................................................................................... ......48 3-4 memory map ( pd789445, 789455) .............................................................................................................. .49 3-5 memory map ( pd789446, 789456) .............................................................................................................. .50 3-6 memory map ( pd78f 9456) ..................................................................................................................... ......51 3-7 data memory addressing ( pd789425, 789435) ............................................................................................54 3-8 data memory addressing ( pd789426, 789436) ............................................................................................55 3-9 data memory addressing ( pd78f9436) ........................................................................................................56 3-10 data memory addressing ( pd789445, 789455) ............................................................................................57 3-11 data memory addressing ( pd789446, 789456) ............................................................................................58 3-12 data memory addressing ( pd78f9456) ........................................................................................................59 3-13 program counter configur ation............................................................................................ ...........................60 3-14 program status word confi guratio n........................................................................................ ........................60 3-15 stack pointe r configur ation.............................................................................................. ...............................62 3-16 data to be sa ved to sta ck memory......................................................................................... ........................62 3-17 data to be rest ored from st ack me mory .................................................................................... ....................62 3-18 general-purpose regi ster confi guratio n................................................................................... ......................63 4-1 port types ( pd789426, 789436 subs eries) ..................................................................................................76 4-2 port types ( pd789446, 789456 subs eries) ..................................................................................................77 4-3 block diagram of p00 to p03 ............................................................................................... ...........................80 4-4 block diagram of p10 and p 11.............................................................................................. ..........................81 4-5 block diagr am of p20...................................................................................................... ................................82 4-6 block diagram of p21 and p 26.............................................................................................. ..........................83 4-7 block diagr am of p22...................................................................................................... ................................84 4-8 block diagr am of p23...................................................................................................... ................................85 4-9 block diagr am of p24...................................................................................................... ................................86 4-10 block diagr am of p25..................................................................................................... .................................87 4-11 block diagr am of p30..................................................................................................... .................................88 4-12 block diagram of p31 to p33 .............................................................................................. ............................89 4-13 block diagram of p50 to p53 .............................................................................................. ............................90 4-14 block diagram of port 6.................................................................................................. .................................91 4-15 block diagram of p70 to p72 .............................................................................................. ............................92 4-16 block diagram of p80 and p 81............................................................................................. ...........................93 4-17 block diagram of p90 to p97 .............................................................................................. ............................94 4-18 format of po rt mode r egister ............................................................................................. ............................96
18 user?s manual u15075ej2v1ud list of figures (2/6) figure no. title page 4-19 format of pull-up resi stor option r egister 0............................................................................. .....................97 4-20 format of pull-up resi stor option r egister b2 ............................................................................ ...................98 4-21 format of pull-up resi stor option r egister b3 ............................................................................ ...................98 4-22 format of pull-up resi stor option r egister b7 ............................................................................ ...................99 4-23 format of pull-up resi stor option r egister b8 ............................................................................ ...................99 4-24 format of pull-up resi stor option r egister b9 ............................................................................ .................100 5-1 block diagram of clock g enerat or .......................................................................................... ......................103 5-2 format of processo r clock contro l regi ster ................................................................................ .................105 5-3 format of subosc illation mode regist er .................................................................................... ....................106 5-4 format of subclo ck control regist er ....................................................................................... ......................107 5-5 external circuit of main system clo ck oscillator (crystal/c eramic o scillati on)............................................ .108 5-6 external circuit of main s ystem clock oscillato r (rc osc illati on) ......................................................... ........109 5-7 external circuit of subsystem clock oscilla tor............................................................................ ..................109 5-8 examples of incorrect connecti on for crystal/ceram ic osc illati on .......................................................... ......110 5-9 examples of incorrect connection for rc oscilla tion ....................................................................... .............112 5-10 switching between system clock and cp u clock (crystal/ceram ic oscilla tion) ..........................................117 5-11 switching between system clock and cpu clock ( rc oscilla tion) ............................................................ ..118 6-1 block diagram of 16-bit timer 90.......................................................................................... ........................121 6-2 format of 16-bit timer mode control r egister 90 ........................................................................... ..............124 6-3 format of buzzer out put control r egister 90............................................................................... .................125 6-4 format of port mode register s 2, 3........................................................................................ .......................126 6-5 settings of 16-bit timer mode control r egister 90 for timer in terrupt oper ation .........................................12 7 6-6 timing of timer interrupt o peratio n....................................................................................... ........................128 6-7 settings of 16-bit timer mode control r egister 90 for timer ou tput oper ation ............................................12 9 6-8 timer ou tput ti ming....................................................................................................... ...............................129 6-9 settings of 16-bit timer mode contro l register 90 for c apture oper ation ................................................... .130 6-10 capture operation timing (both edges of cp t90 pin are specif ied) ......................................................... ..130 6-11 16-bit timer count er 90 readout timing ................................................................................... ...................131 6-12 settings of buzzer output control r egister 90 for buzzer output o peration ................................................ 132 7-1 block diagram of ti mer 50 ................................................................................................. ...........................139 7-2 block diagram of ti mer 60 ................................................................................................. ...........................140 7-3 block diagram of out put controller (timer 60)............................................................................. .................141 7-4 format of 8-bit timer mode control r egister 50 ............................................................................ ...............145 7-5 format of 8-bit timer mode control r egister 60 ............................................................................ ...............147 7-6 format of carrier generator output contro l regist er 60.................................................................... ...........148 7-7 format of port mode regi ster 3 ............................................................................................ ........................149
user?s manual u15075ej2v1ud 19 list of figures (3/6) figure no. title page 7-8 timing of interval timer operation with 8-bit resolution (basic o perati on) ................................................ ..152 7-9 timing of interval timer operation with 8-bit resolution (when cr n0 is set to 00h) ..................................152 7-10 timing of interval timer operation with 8-bit resolution (when cr n0 is set to ffh)..................................153 7-11 timing of interval timer operation with 8- bit resolution (when crn0 changes from n to m (n < m)) ........153 7-12 timing of interval timer operation with 8- bit resolution (when crn0 changes from n to m (n > m)) ........154 7-13 timing of interval timer operation with 8-bit resolution (when timer 60 match signal is selected for timer 50 c ount clo ck)......................................................................................................... ..........................154 7-14 timing of operation of external event counter with 8-bit reso luti on...................................................... ......155 7-15 timing of square-wave ou tput with 8-bi t resolu tion....................................................................... .............157 7-16 timing of interval timer operation with 16- bit reso lution................................................................ .............160 7-17 timing of external event count er operation with 16-bit reso luti on........................................................ ......162 7-18 timing of square-wave ou tput with 16-bi t resolu tion...................................................................... ............164 7-19 timing of carrier generator operation (when cr60 = n, crh60 = m (m > n)) ...........................................167 7-20 timing of carrier generator operation (when cr60 = n, crh60 = m (m < n) ............................................168 7-21 timing of carrier generator operation (when cr60 = crh 60 = n)............................................................ .169 7-22 operation timing in pwm free-runni ng mode (when rising e dge is sele cted) .........................................171 7-23 operation timing w hen overwriting cr50 (when ris ing edge is select ed) ................................................ 171 7-24 operation timing in pwm free-runni ng mode (when both edges are sele cted) .......................................172 7-25 operation timing in pwm free-runni ng mode (when both edges are selected) (when cr50 is overwri tten) .................................................................................................... .....................173 7-26 pwm pulse generator m ode timing (basic operat ion) ........................................................................ ........175 7-27 pwm output mode timing (when cr60 and crh60 are ov erwritt en) ........................................................ 175 7-28 start timing of 8-bit time r count er ...................................................................................... .........................176 7-29 timing of operation as external event counter (8 -bit reso luti on)......................................................... .......176 8-1 block diagram of watch timer.............................................................................................. ........................177 8-2 format of watch time r mode contro l regi ster ............................................................................... ..............179 8-3 watch timer/interval timer operat ion ti ming............................................................................... ................181 9-1 block diagram of watchdog timer ........................................................................................... .....................183 9-2 format of watchdog time r clock select regi ster............................................................................ .............184 9-3 format of watchdog timer mode regist er.................................................................................... ................185 10-1 block diagram of 8-bit a/d c onverter ..................................................................................... ......................189 10-2 format of a/d conv erter mode r egister 0 .................................................................................. ..................191 10-3 format of analog input channel specification register 0 .................................................................. ...........192 10-4 basic operation of 8-bit a/d conver ter ................................................................................... ......................194 10-5 relationship between analog input voltage and a/d c onversion resu lt...................................................... 195 10-6 software-start ed a/d conv ersion.......................................................................................... ........................196
20 user?s manual u15075ej2v1ud list of figures (4/6) figure no. title page 10-7 how to reduce current consumption in standby mode ........................................................................ .......197 10-8 conversion result read timing ( if conversion result is u ndefi ned)........................................................ ....198 10-9 conversion result read timing (if conversion resu lt is norma l) ........................................................... .....198 10-10 analog input pin tr eatment .............................................................................................. .............................199 10-11 a/d conversion end interr upt request gener ation ti ming .................................................................. .........200 10-12 av dd pin h andlin g .................................................................................................................. .......................200 11-1 block diagram of 10-bit a/d c onverter .................................................................................... .....................202 11-2 format of a/d conv erter mode r egister 0 .................................................................................. ..................204 11-3 format of analog input channel specification register 0 .................................................................. ...........205 11-4 basic operation of 10-bit a/d conver ter .................................................................................. .....................207 11-5 relationship between analog input voltage and a/d c onversion resu lt ...................................................... 208 11-6 software-start ed a/d conv ersion.......................................................................................... ........................209 11-7 how to reduce current consumption in standby mode ........................................................................ .......210 11-8 conversion result read timing ( if conversion result is u ndefi ned)........................................................ ....211 11-9 conversion result read timing (if conversion resu lt is norma l) ........................................................... .....211 11-10 analog input pin tr eatment .............................................................................................. .............................212 11-11 a/d conversion end interr upt request gener ation ti ming .................................................................. .........213 11-12 av dd pin h andlin g .................................................................................................................. .......................213 12-1 block diagram of serial inte rface 20 ..................................................................................... ........................215 12-2 block diagram of baud rate g enerator 20 .................................................................................. .................216 12-3 format of serial o peration mode r egister 20 .............................................................................. .................218 12-4 format of asynchronous seri al interface m ode regist er 20 ................................................................. ........219 12-5 format of asynchronous serial interface status regist er 20 ............................................................... .........221 12-6 format of baud rate gener ator control register 20........................................................................ .............222 12-7 format of asynchronous serial interface transmi t/receive data ............................................................ .....234 12-8 asynchronous serial interface tr ansmission completion interrupt timing................................................... .236 12-9 asynchronous serial interface re ception completion interrupt timing...................................................... ...237 12-10 receive error ti ming .................................................................................................... .................................238 12-11 3-wire seri al i/o mode timing ........................................................................................... ...........................244 13-1 block diagram of lcd controlle r/driv er ................................................................................... .....................252 13-2 format of lcd displ ay mode regi ster 0 .................................................................................... ...................254 13-3 format of lcd clock control regi ster 0 ................................................................................... ....................255 13-4 format of lcd voltage amplif ication control register 0 ................................................................... ............256 13-5 relationship between lcd display data memory contents and segment/common outputs ( pd789446, 789456 s ubserie s) .................................................................................................... ..............257 13-6 common si gnal wave forms .................................................................................................. ........................259
user?s manual u15075ej2v1ud 21 list of figures (5/6) figure no. title page 13-7 voltages and phases of common and segm ent si gnals ......................................................................... .....259 13-8 three-time slot lcd displ ay pattern and el ectrode c onnecti ons............................................................ ....260 13-9 example of connecting th ree-time slot lcd panel .......................................................................... ...........261 13-10 three-time slot l cd drive wavefo rm exam ples ............................................................................. ............262 13-11 four-time slot lcd display pattern and elec trode connec tions............................................................ ......263 13-12 example of connecting four-time slot lcd panel .......................................................................... .............264 13-13 four-time slot lcd drive wavefo rm exam ples .............................................................................. .............265 13-14 example of connecti ng pins for lcd dr iver............................................................................... ...................266 14-1 basic configuration of interrupt func tion ................................................................................ ......................269 14-2 format of interrupt request flag regist ers ............................................................................... ...................271 14-3 format of interrupt mask flag r egisters .................................................................................. .....................272 14-4 format of external in terrupt mode r egister 0 ............................................................................. ..................273 14-5 format of external in terrupt mode r egister 1 ............................................................................. ..................274 14-6 configuration of program stat us word..................................................................................... .....................274 14-7 format of key retu rn mode regi ster 00 .................................................................................... ...................275 14-8 block diagram of falling edge detect or................................................................................... .....................275 14-9 flow from generation of non-mask able interrupt request to ackno wledgment ...........................................277 14-10 timing of non-maskable in terrupt request acknowl edgment ................................................................. ......277 14-11 non-maskable interr upt request a cknowl edgment ........................................................................... ............277 14-12 interrupt request ackno wledgment program algor ithm...................................................................... ..........278 14-13 interrupt request acknowledgm ent timing (examp le: mov a, r) ............................................................. ....279 14-14 interrupt request acknowledgment timing (when interrupt request flag is generated in final clock under execut ion) ........................................................................................................ .........................279 14-15 example of mu ltiple in terrupts .......................................................................................... .............................280 15-1 format of oscillation stabiliz ation time sele ct regi ster ................................................................. ..............283 15-2 releasing halt mode by interr upt ......................................................................................... ......................285 15-3 releasing halt mode by r eset i nput....................................................................................... .................286 15-4 releasing stop mode by interr upt......................................................................................... ......................288 15-5 releasing stop mode by r eset i nput ....................................................................................... ................289 16-1 block diagram of reset function .......................................................................................... ........................290 16-2 reset timing by reset input.............................................................................................. .........................291 16-3 reset timing by over flow in wa tchdog ti mer ............................................................................... ...............291 16-4 reset timing by reset input in stop mode ................................................................................. .............291
22 user?s manual u15075ej2v1ud list of figures (6/6) figure no. title page 17-1 environment for writi ng program to flash me mory .......................................................................... .............295 17-2 communication m ode selecti on forma t...................................................................................... ..................296 17-3 example of connection with dedicated flas h progra mmer.................................................................... .......297 17-4 v pp pin connecti on exam ple........................................................................................................ .................299 17-5 signal conflict (seria l interface input pin) ............................................................................. ........................300 17-6 malfunction of another device............................................................................................ ...........................300 17-7 signal conf lict (reset pin) .............................................................................................. ............................301 17-8 wiring example for flash writi ng adapter using 3- wire se rial i/o......................................................... .......302 17-9 wiring example for flash writing adapter using uart ...................................................................... ..........303 a-1 developm ent t ools......................................................................................................... ...............................341 b-1 distance between in-circuit emulator and conversion adapter (when 64gb is used) ................................346 b-2 connection conditions of target system (when np-64g b-tq is used) ......................................................347 b-3 connection conditions of target system (when np-h64g b-tq is used) ....................................................347 b-4 distance between in-circuit emulator and conversion adapter (w hen 64gk is used) ................................348 b-5 connection conditions of target system (when np- 64gk is used) ............................................................3 48 b-6 connection conditions of target system (when np-h64g k-tq is used) ....................................................349
user?s manual u15075ej2v1ud 23 list of tables (1/2) table no. title page 2-1 types of pin i nput/output circuits ........................................................................................ ...........................44 3-1 internal rom capac ity ..................................................................................................... ...............................52 3-2 vector table .............................................................................................................. ......................................52 3-3 lcd display ram c apacity.................................................................................................. ...........................53 3-4 special functi on register list ............................................................................................ .............................65 4-1 port functi ons ............................................................................................................ .....................................78 4-2 configurat ion of port..................................................................................................... ...................................79 4-3 port mode register and output latch settings when using al ternate f unctions ...........................................97 5-1 configuration of clock g enerat or .......................................................................................... ........................102 5-2 maximum time required for switching cpu clo ck (when crystal/ceramic o scillation is select ed) ...........116 5-3 maximum time required for switching cpu clock (when rc oscilla tion is se lected) ................................116 6-1 16-bit timer 90 configur ation............................................................................................. ...........................120 6-2 interval time of 16-bit timer 90 .......................................................................................... ..........................127 6-3 settings of captur e edge .................................................................................................. ............................130 6-4 buzzer frequency of 16-bit ti mer 90 ....................................................................................... .....................132 7-1 operat ion m odes ........................................................................................................... ................................137 7-2 8-bit timer configur ation................................................................................................. ..............................138 7-3 interval ti me of ti mer 50................................................................................................. ..............................151 7-4 interval ti me of ti mer 60................................................................................................. ..............................151 7-5 square-wave output range of timer 50 (during f x = 5.0 mhz o perati on)................................................... 156 7-6 square-wave output range of timer 60 (during f x = 5.0 mhz o perati on)................................................... 157 7-7 interval time with 16-bit resolution (during f x = 5.0 mhz o perati on)........................................................... 159 7-8 square-wave output range with 16-bit resolution (during f x = 5.0 mhz o perati on) .................................. 163 8-1 interval generated us ing the interv al timer............................................................................... ...................178 8-2 watch timer configur ation................................................................................................. ...........................178 8-3 interval time of interval timer........................................................................................... ............................180 9-1 watchdog timer runaw ay detect ion ti me ..................................................................................... ..............182 9-2 interv al time.............................................................................................................. ....................................182 9-3 configuration of watchdog timer ........................................................................................... .......................183 9-4 watchdog timer runaw ay detect ion ti me ..................................................................................... ..............186 9-5 interval time of interval timer........................................................................................... ............................187 10-1 configuration of 8-bit a/d c onverter ..................................................................................... ........................188
24 user?s manual u15075ej2v1ud list of tables (2/2) table no. title page 11-1 configuration of 10-bit a/d c onverter .................................................................................... .......................201 12-1 configuration of serial inte rface 20 ..................................................................................... ..........................214 12-2 serial interface 20 operating mode se ttings .............................................................................. ...................220 12-3 example of relationships between system clo ck and baud rate.............................................................. ..223 12-4 relationship between asck20 pin input frequen cy and baud rate (when brgc 20 is set to 80h) ..........224 12-5 example of relationships between system clo ck and baud rate.............................................................. ..232 12-6 relationship between asck20 pin input frequen cy and baud rate (when brgc 20 is set to 80h) ..........233 12-7 receive error c auses..................................................................................................... ...............................238 13-1 number of segment output s and maximum num ber of pixe ls ................................................................... ..251 13-2 configuration of lcd controlle r/driv er ................................................................................... .......................251 13-3 frame fr equencies (hz)................................................................................................... .............................255 13-4 com signal s .............................................................................................................. ...................................258 13-5 select and deselect voltages (com0 to com2).............................................................................. .............260 13-6 select and deselect voltages (com0 to com3).............................................................................. .............263 13-7 output voltages of v lc0 to v lc2 pins .............................................................................................................266 14-1 interrupt source list .................................................................................................... ..................................268 14-2 flags corresponding to in terrupt request signal name ..................................................................... ..........270 14-3 time from generation of mask able interrupt reques t to serv icing .......................................................... .....278 15-1 halt mode o perating status............................................................................................... .........................284 15-2 operation after releasing ha lt mode ...................................................................................... ...................286 15-3 stop mode o perating status ............................................................................................... ........................287 15-4 operation after releasing st op mode...................................................................................... ...................289 16-1 hardware stat us after reset ............................................................................................. ...........................292 17-1 differences between pd78f9436, 78f9456 and mask rom vers ions .......................................................294 17-2 communica tion mode list .................................................................................................. ...........................296 17-3 pin c onnection list...................................................................................................... ..................................298 19-1 operand identifiers and descripti on met hods.............................................................................. ..................305 23-1 surface mounting ty pe soldering conditi ons .............................................................................. .................337 b-1 distance between ie s ystem and conver sion a dapter ......................................................................... ........346
user?s manual u15075ej2v1ud 25 chapter 1 general 1.1 features rom and ram capacities item data memory part number program memory internal high-speed ram lcd display ram pd789425, 789435 8 kb pd789426, 789436 mask rom 16 kb pd78f9436 flash memory 16 kb 5 bytes pd789445, 789455 12 kb pd789446, 789456 mask rom pd78f9456 flash memory 16 kb 512 bytes 15 bytes crystal/ceramic oscillation or rc oscillation is selectable for the oscillator by a mask option. minimum instruction execution ti me can be changed from high-speed (0.4 s: @ 5.0 mhz operation with main system clock) to ultra-low-speed (122 s: @ 32.768 khz operation with subsyst em clock) (crystal/ceramic oscillation) minimum instruction execution ti me can be changed from high-speed (0.5 s: @ 4.0 mhz operation with main system clock) to ultra-low-speed (122 s: @ 32.768 khz operation with sub system clock) (rc oscillation) i/o ports: 40 ( pd789426, 789436 subseries) 30 ( pd789446, 789456 subseries) timer: 5 channels 16-bit timer: 1 channel 8-bit timer: 2 channels watch timer: 1 channel watchdog timer: 1 channel a/d converter: 8-bit resolution: 6 channels ( pd789426, 789446 subseries) 10-bit resolution: 6 channels ( pd789436, 789456 subseries) serial interface: 1 channel lcd controller/driver segment signals: 5, common signals: 4 ( pd789426, 789436 subseries) segment signals: 15, common signals: 4 ( pd789446, 789456 subseries) vectored interrupt sources: 15 power supply voltage: v dd = 1.8 to 5.5 v operating ambient temperature: t a = ?40 to +85 c 1.2 applications portable audio, cameras, healthcare equipment, etc.
chapter 1 general 26 user?s manual u15075ej2v1ud 1.3 ordering information part number package internal rom pd789425gk- -9et 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789426gk- -9et 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789435gk- -9et 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789436gk- -9et 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789445gk- -9et 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789446gk- -9et 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789455gk- -9et 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789456gk- -9et 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789425gb- -8eu 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789426gb- -8eu 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789435gb- -8eu 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789436gb- -8eu 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789445gb- -8eu 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789446gb- -8eu 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789455gb- -8eu 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789456gb- -8eu 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd78f9436gk-9et 64-pin plastic tqfp (fine pitch) (12 12) flash memory pd78f9456gk-9et 64-pin plastic tqfp (fine pitch) (12 12) flash memory pd78f9436gb-8eu 64-pin plastic lqfp (fine pitch) (10 10) flash memory pd78f9456gb-8eu 64-pin plastic lqfp (fine pitch) (10 10) flash memory pd789425gk- -9et-a 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789426gk- -9et-a 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789435gk- -9et-a 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789436gk- -9et-a 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789445gk- -9et-a 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789446gk- -9et-a 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789455gk- -9et-a 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789456gk- -9et-a 64-pin plastic tqfp (fine pitch) (12 12) mask rom pd789425gb- -8eu-a 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789426gb- -8eu-a 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789435gb- -8eu-a 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789436gb- -8eu-a 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789445gb- -8eu-a 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789446gb- -8eu-a 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789455gb- -8eu-a 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd789456gb- -8eu-a 64-pin plastic lqfp (fine pitch) (10 10) mask rom pd78f9436gk-9et-a 64-pin plasti c tqfp (fine pitch) (12 12) flash memory pd78f9456gk-9et-a 64-pin plasti c tqfp (fine pitch) (12 12) flash memory pd78f9436gb-8eu-a 64-pin plasti c lqfp (fine pitch) (10 10) flash memory pd78f9456gb-8eu-a 64-pin plasti c lqfp (fine pitch) (10 10) flash memory remarks 1. products that have the part numbers suffi xed by "-a" are lead-free products. 2. indicates rom code suffix.
chapter 1 general user?s manual u15075ej2v1ud 27 1.4 pin configuration (top view) 1.4.1 pin configuration of pd789426, 789436 subseries (top view) ? 64-pin plastic tqfp (fine pitch) (12 12) pd789425gk- -9et pd789425gk- -9et-a pd78f9436gk-9et pd789426gk- -9et pd789426gk- -9et-a pd78f9436gk-9et-a pd789435gk- -9et pd789435gk- -9et-a pd789436gk- -9et pd789436gk- -9et-a ? 64-pin plastic lqfp (fine pitch) (10 10) pd789425gb- -8eu pd789425gb- -8eu-a pd78f9436gb-8eu pd789426gb- -8eu pd789426gb- -8eu-a pd78f9436gb-8eu-a pd789435gb- -8eu pd789435gb- -8eu-a pd789436gb- -8eu pd789435gb- -8eu-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p50 p51 p52 p53 ic(v pp ) xt1 xt2 v dd v ss x1 [cl1] x2 [cl2] reset p00/kr0 p01/kr1 p02/kr2 p03/kr3 32 caph capl v lc0 v lc1 v lc2 com0 com1 com2 com3 s0 s1 s2 s3 s4 p90 p91 p62/ani2 p63/ani3 p64/ani4 p65/ani5 av dd p72 p71 p70 p81 p80 p97 p96 p95 p94 p93 p92 p20 p21/bzo90 p22/ss20 p23/sck20/asck20 p24/so20/txd20 p25/si20/rxd20 p26/to90 p30/intp0/cpt90 p31/intp1/to50/tmi60 p32/intp2/to60 p33/intp3/to61 p10 p11 av ss p60/ani0 p61/ani1 cautions 1. connect the ic (inter nally connected) pin directly to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . remarks 1. the items in parentheses apply to the pd78f9436. 2. the items in brackets apply when rc oscillation is selected (mask option).
chapter 1 general 28 user?s manual u15075ej2v1ud 1.4.2 pin configuration of pd789446, 789456 subseries (top view) ? 64-pin plastic tqfp (fine pitch) (12 12) pd789445gk- -9et pd789445gk- -9et-a pd78f9456gk-9et pd789446gk- -9et pd789446gk- -9et-a pd78f9456gk-9et-a pd789455gk- -9et pd789455gk- -9et-a pd789456gk- -9et pd789456gk- -9et-a ? 64-pin plastic lqfp (fine pitch) (10 10) pd789445gb- -8eu pd789445gb- -8eu-a pd78f9456gb-8eu pd789446gb- -8eu pd789446gb- -8eu-a pd78f9456gb-8eu-a pd789455gb- -8eu pd789455gb- -8eu-a pd789456gb- -8eu pd789455gb- -8eu-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p50 p51 p52 p53 ic(v pp ) xt1 xt2 v dd v ss x1 [cl1] x2 [cl2] reset p00/kr0 p01/kr1 p02/kr2 p03/kr3 32 caph capl v lc0 v lc1 v lc2 com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 p62/ani2 p63/ani3 p64/ani4 p65/ani5 av dd p72 p71 p70 s14 s13 s12 s11 s10 s9 s8 s7 p20 p21/bzo90 p22/ss20 p23/sck20/asck20 p24/so20/txd20 p25/si20/rxd20 p26/to90 p30/intp0/cpt90 p31/intp1/to50/tmi60 p32/intp2/to60 p33/intp3/to61 p10 p11 av ss p60/ani0 p61/ani1 cautions 1. connect the ic (inter nally connected) pin directly to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . remarks 1. the items in parentheses apply to the pd78f9456. 2. the items in brackets apply when rc oscillation is selected (mask option).
chapter 1 general user?s manual u15075ej2v1ud 29 pin name ani0 to ani5: analog input p80, p81 note 1 : port 8 asck20: asynchronous serial input p90 to p97 note 1 : port 9 av dd : analog power supply reset: reset av ss : analog ground rxd20: receive data bzo90: buzzer output ss20: serial chip select caph, capl: lcd power supply capacitanc e control s0 to s4, s5 to s14 note 2 : segment output cl1, cl2: rc oscillator (main system clock) sck20: serial clock com0 to com3: common out put si20: serial input cpt90: capture trigger i nput so20: serial output ic: internally connected tmi60: timer input intp0 to intp3: external inte rrupt input to90, to50, to60, kr0 to kr3: key return to61: timer output p00 to p03: port 0 txd20: transmit data p10, p11: port 1 v dd : power supply p20 to p26: port 2 v lc0 to v lc2 : lcd power supply p30 to p33: port 3 v pp : programming power supply p50 to p53: port 5 v ss : ground p60 to p65: port 6 x1, x2: crystal (main system clock) p70 to p72: port 7 xt1, xt 2: crystal (subsystem clock) notes 1. pd789426, 789436 subseries only 2. pd789446, 789456 subseries only
chapter 1 general 30 user?s manual u15075ej2v1ud 1.5 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 4) 52-pin 52-pin sio and resistance division type lcd (24 4) 8-bit a/d and on-chip voltage booster type lcd (23 4) pd789327 pd789467 pd789446 pd789436 pd789426 pd789306 pd789316 pd789426 with enhanced a/d converter (10 bits) pd789446 with enhanced a/d converter (10 bits) sio, 8-bit a/d, and on-chip voltage booster type lcd (15 4) sio, 8-bit a/d, and on-chip voltage booster type lcd (5 4) rc oscillation version of the pd789306 sio and on-chip voltage booster type lcd (24 4) 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin pd789407a pd789456 lcd drive 80-pin pd789417a pd789407a with enhanced a/d converter (10 bits) sio, 10-bit a/d converter, and on-chip voltage booster type lcd (28 4) 80-pin sio, 8-bit a/d converter, and resistance division type lcd (28 4) 80-pin pd789478 pd789488 pd789881 64-pin uart and resistance division type lcd (26 4) products under development products in mass production pd789014 small-scale package, general-purpose applications 78k/0s series 28-pin pd789014 with enhanced timer and increased rom, ram capacity on-chip uart and capable of low voltage (1.8 v) operation pd789074 with added subsystem clock pd789146 pd789156 44-pin small-scale package, general-purpose applications and a/d converter 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 30-pin 30-pin pd789104a pd789114a pd789167 with enhanced a/d converter (10 bits) pd789104a with enhanced timer pd789124a with enhanced a/d converter (10 bits) rc oscillation version of the pd789104a pd789104a with enhanced a/d converter (10 bits) pd789026 with added 8-bit a/d converter and multiplier pd789104a with added eeprom pd789146 with enhanced a/d converter (10 bits) pd789177y pd789167y y subseries products support smb. 88-pin pd789830 pd789835 144-pin uart and dot lcd (40 16) uart, 8-bit a/d, and dot lcd (total display output pins: 96) 42-/44-pin 44-pin pd789074 30-pin pd789026 with enhanced timer 30-pin pd789074 with enhanced timer and increased rom, ram capacity pd789088 pd789046 pd789026 usb 44-pin pd789800 for pc keyboard and on-chip usb function inverter control 44-pin pd789842 on-chip inverter controller and uart vfd drive 52-pin pd789871 on-chip vfd controller (total display output pins: 25) keyless entry 20-pin pd789860 pd789861 20-pin on-chip poc and key return circuit rc oscillation version of the pd789860 on-chip bus controller pd789850a on-chip can controller meter control pd789052 20-pin pd789860 without eeprom tm , poc, and lvi pd789062 20-pin rc oscillation version of the pd789052 pd789862 30-pin 30-pin 44-pin pd789860 with enhanced timer, added sio, and increased rom, ram capacity pd789852 pd789850a with enhanced functions such as timer and a/d converter ? ? remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same.
chapter 1 general user?s manual u15075ej2v1ud 31 the major functional differences bet ween the subseries are listed below. series for general-purpose applications and lcd drive timer v dd function subseries name rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks pd789046 16 kb 1 ch pd789026 4 kb to 16 kb 1 ch 34 pd789088 16 kb to 32 kb 3 ch pd789074 2 kb to 8 kb 1 ch 1 ch 24 pd789014 2 kb to 4 kb 1 ch (uart: 1 ch) 22 ? pd789062 rc oscillation version small-scale package, general- purpose applications pd789052 4 kb 2 ch ? ? 1 ch ? ? ? 14 1.8 v ? pd789177 ? 8 ch pd789167 16 kb to 24 kb 3 ch 1 ch 8 ch ? 31 ? pd789156 ? 4 ch pd789146 8 kb to 16 kb 4 ch ? on-chip eeprom pd789134a ? 4 ch pd789124a 4 ch ? rc oscillation version pd789114a ? 4 ch small-scale package, general- purpose applications and a/d converter pd789104a 2 kb to 8 kb 1 ch 1 ch ? 1 ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? pd789835 24 kb to 60 kb 6 ch ? 3 ch 37 1.8 v note pd789830 24 kb 1 ch ? 1 ch (uart: 1 ch) 30 2.7 v dot lcd supported pd789488 32 kb to 48 kb ? 8 ch pd789478 24 kb to 48 kb 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 kb to 24 kb 3 ch 7 ch ? 43 pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 kb to 16 kb 6 ch 1 ch (uart: 1 ch) 40 ? pd789316 rc oscillation version pd789306 8 kb to 16 kb 1 ch ? 2 ch (uart: 1 ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 kb to 24 kb 2 ch ? 1 ch 1 ch ? ? 1 ch 21 1.8 v ? note flash memory version: 3.0 v
chapter 1 general 32 user?s manual u15075ej2v1ud series for assp timer v dd function subseries name rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks usb pd789800 8 kb 2 ch ? ? 1 ch ? ? 2 ch (usb: 1 ch) 31 4.0 v ? inverter control pd789842 8 kb to 16 kb 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? pd789852 24 kb to 32 kb 3 ch ? 8 ch 3 ch (uart: 2 ch) 31 on-chip bus controller pd789850a 16 kb 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1 ch) 18 4.0 v ? pd789861 rc oscillation version, on- chip eeprom pd789860 4 kb 2 ch ? ? 14 keyless entry pd789862 16 kb 1 ch 2 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 22 1.8 v on-chip eeprom vfd drive pd789871 4 kb to 8 kb 3 ch ? 1 ch 1 ch ? ? 1 ch 33 2.7 v ? meter control pd789881 16 kb 2 ch 1 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 28 2.7 v note 2 ? notes 1. 10-bit timer: 1 channel 2. flash memory version: 3.0 v
chapter 1 general user?s manual u15075ej2v1ud 33 1.6 block diagram 1.6.1 block diagram of pd789426, 789436 subseries v dd v ss ic (v pp ) 78k/0s cpu core rom (flash memory) to50/tmi60/ p31 8-bit timer 50 p00 to p03 port 0 p10, p11 port 1 p20 to p26 port 2 p30 to p33 port 3 tmi60/to50/ p31 16-bit timer 90 watch timer watchdog timer to90/p26 s0 to s4 com0 to com3 ram ram space for lcd data 8-bit timer/event counter 60 cascaded 16-bit timer/ event counter to60/p32 cpt90/p30 v lc0 to v lc2 caph capl lcd controller driver p50 to p53 port 5 system control reset x1 [cl1] x2 [cl2] xt1 xt2 interrupt control intp0/p30 intp1/p31 intp2/p32 intp3/p33 kr0/p00 to kr3/p03 to61/p33 bzo90/p21 serial interface 20 sck20/asck20/p23 si20/rxd20/p25 so20/txd20/p24 ss20/p22 a/d converter ani0/p60 to ani5/p65 av ss av dd p70 to p72 port 7 p60 to p65 port 6 p80, p81 port 8 p90 to p97 port 9 remarks 1. the internal rom capacity varies depending on the product. 2. the items in parentheses apply to the pd78f9436. 3. the items in brackets apply when rc oscillation is selected (mask option).
chapter 1 general 34 user?s manual u15075ej2v1ud 1.6.2 block diagram of pd789446, 789456 subseries v dd v ss ic (v pp ) 78k/0s cpu core rom (flash memory to50/tmi60/ p31 8-bit timer 50 p00 to p03 port 0 p10, p11 port 1 p20 to p26 port 2 p30 to p33 port 3 tmi60/to50/ p31 16-bit timer 90 watch timer watchdog timer to90/p26 s0 to s14 com0 to com3 ram ram space for lcd data 8-bit timer/event counter 60 cascaded 16-bit timer/ event counter to60/p32 cpt90/p30 v lc0 to v lc2 caph capl lcd controller driver p50 to p53 port 5 system control reset x1 [cl1] x2 [cl2] xt1 xt2 interrupt control to61/p33 bzo90/p21 serial interface 20 sck20/asck20/p23 si20/rxd20/p25 so20/txd20/p24 ss20/p22 a/d converter ani0/p60 to ani5/p65 av ss av dd p70 to p72 port 7 p60 to p65 port 6 intp0/p30 intp1/p31 intp2/p32 intp3/p33 kr0/p00 to kr3/p03 remarks 1. the internal rom capacity varies depending on the product. 2. the items in parentheses apply to the pd78f9456. 3. the items in brackets apply when rc oscillation is selected (mask option).
chapter 1 general user?s manual u15075ej2v1ud 35 1.7 overview of functions item pd789425, 789435 pd789426, 789436 pd78f9436 pd789445, 789455 pd789446, 789456 pd78f9456 mask rom flash memory mask rom flash memory rom 12 kb 16 kb 12 kb 16 kb high-speed ram 512 bytes internal memory lcd display ram 5 bytes 15 bytes crystal/ceramic oscillation 0.4 s/1.6 s (@ 5.0 mhz operation with main system clock) rc oscillation note 0.5 s/2.0 s (@ 4.0 mhz operation with main system clock) minimum instruction execution time 122 s (@ 32.768 khz operation with subsystem clock) 8 bits 8 registers instruction set 16-bit operations bit manipulations (such as set, reset, and test) i/o ports total: 40 cmos i/o: 30 cmos input: 6 n-ch open-drain: 4 total: 30 cmos i/o: 20 cmos input: 6 n-ch open-drain: 4 timers 16-bit timer: 1 channel 8-bit timer: 2 channels watch timer: 1 channel watchdog timer: 1 channel a/d converter 8-bit resolution 6 channels ( pd789426, 789446 subseries) 10-bit resolution 6 channels ( pd789436, 789456 subseries) serial interfaces switchable between 3-wire serial i/o mode and uart mode: 1 channel lcd controller/driver segment signal outputs: 5 max. common signal outputs: 4 max. segment signal outputs: 15 max. common signal outputs: 4 max. maskable internal: 9, external: 5 vectored interrupt sources non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to + 85c package 64-pin plastic tqfp (fine pitch) (12 12) 64-pin plastic lqfp (fine pitch) (10 10) note selectable by a mask option. rc o scillation is not possible in the pd78f9436 and 78f9456.
chapter 1 general 36 user?s manual u15075ej2v1ud an outline of the timer is shown below. 16-bit timer 8?bit timer 50 8-bit timer 60 watch timer watchdog timer interval timer ? 1 channel 1 channel 1 channel note 1 1 channel note 2 operation mode external event counter ? ? 1 channel ? ? timer outputs 1 1 2 ? ? square-wave outputs ? 1 2 ? ? capture 1 input ? ? ? ? function interrupt sources 1 1 1 2 2 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has the watchdog timer and interv al timer functions. however, use the watchdog timer by selecting either the watchdog time r function or interval timer function.
user?s manual u15075ej2v1ud 37 chapter 2 pin functions 2.1 list of pin functions (1) port pins (1/2) pin name i/o function after reset alternate function p00 to p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resistor option register 0 (pu0) or key return mode register 00 (krm00). input kr0 to kr3 p10 to p13 i/o port 1. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register 0 (pu0). input ? p20 ? p21 bzo90 p22 ss20 p23 sck20/asck20 p24 so20/txd20 p25 si20/rxd20 p26 i/o port 2. 7-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register b2 (pub2). input to90 p30 intp0/cpt90 p31 intp1/to50/ tmi60 p32 intp2/to60 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register b3 (pub3). input intp3/to61 p50 to p53 i/o port 5. 4-bit n-ch open-drain i/o port. input/output can be specified in 1-bit units. for a mask rom version, an on-chip pull-up resistor can be specified by the mask option. input ? p60 to p65 input port 6. 6-bit input port. input ani0 to ani5 p70 to p72 i/o port 7. 3-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register b7 (pub7). input ?
chapter 2 pin functions 38 user?s manual u15075ej2v1ud (1) port pins (2/2) pin name i/o function after reset alternate function p80, p81 note i/o port 8. 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register b8 (pub8). input ? p90 to p97 note i/o port 9. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by setting pull-up resist or option register b9 (pub9). input ? note pd789426, 789436 subseries only
chapter 2 pin functions user?s manual u15075ej2v1ud 39 (2) non-port pins pin name i/o function after reset alternate function intp0 p30/cpt90 intp1 p31/to50/tmi60 intp2 p32/to60 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p33/to61 kr0 to kr3 input key return signal detection input p00 to p03 ss20 input serial interface (sio20) chip select input p22 sck20 i/o serial interface 20 serial clock input/output input p23/asck20 si20 input serial interface 20 of sio20 serial data input input p25/rxd20 so20 output serial interface 20 of sio20 serial data output input p24/txd20 asck20 input serial clock i nput for asynchronous serial interface input p23/sck20 rxd20 input serial data input for asynch ronous serial interface input p25/si20 txd20 output serial data output for asyn chronous serial interface input p24/so20 to90 output 16-bit timer (tm90) output input p26 cpt90 input capture edge input input p30/intp0 to50 output 8-bit timer (tm50) output input p31/intp1/tmi40 to60 output input p32/intp2 to61 output 8-bit timer (tm60) output input p33/intp33 tmi60 input external count clock i nput to timer 40 input p31/intp1/to50 ani0 to ani5 input a/d converter analog input input p60 to p65 s0 to s4 output output ? s5 to s14 note 1 output lcd controller/driver segment signal output output ? com0 to com3 output lcd controller/driver common signal output output ? v lc0 to v lc2 ? lcd driving voltage ? ? caph ? ? ? capl ? capacitor connection pin for lcd drive ? ? x1 input ? ? x2 ? connecting crystal resonator for main system clock oscillation ? ? cl1 note 2 input ? ? cl2 note 2 ? connection of resonator (r) and capacitor (c) for main system clock oscillation. ? ? xt1 input ? ? xt2 ? connecting crystal resonator fo r subsystem clock oscillation ? ? reset input system reset input input ? v dd ? positive power supply ? ? v ss ? ground potential ? ? av dd ? a/d converter analog potential ? av ss ? a/d converter analog ground potential ? ? ic ? internally connected. connect directly to v ss . ? ? v pp ? sets flash memory programming mode. applies high voltage when a program is written or verified. ? ? notes 1. pd789446, 789456 subseries only 2. in case of rc oscillation (mask option) only
chapter 2 pin functions 40 user?s manual u15075ej2v1ud 2.2 description of pin functions 2.2.1 p00 to p03 (port 0) these pins constitute a 4-bit i/o port. in additi on, these pins enable key return signal detection. port 0 can be specified in the follo wing operation modes in 1-bit units. (1) port mode these pins constitute a 4-bit i/o port and can be set in the input or output port m ode in 1-bit units by port mode register 0 (pm0). when used as an input port, use of an on-chip pu ll-up resistor can be specified by setting pull-up resistor option register 0 (pu0) in port units. (2) control mode in this mode, p00 to p03 function as key return signal detection pins (kr0 to kr3). 2.2.2 p10, p11 (port 1) these pins constitute a 2-bit i/o port and can be set in t he input or output port mode in 1-bit units by port mode register 1 (pm1). when used as an i nput port, use of an on-chip pull-up resist or can be specified by setting pull-up resistor option register 0 (pu0) in port units. 2.2.3 p20 to p26 (port 2) these pins constitute a 7-bit i/o port. in addition, thes e pins enable buzzer output, timer output, serial interface data i/o, and serial clock i/o. port 2 can be specified in the follo wing operation modes in 1-bit units. (1) port mode in this mode, p20 to p26 function as a 7-bit i/o port. port 2 can be set in the i nput or output port mode in 1- bit units by port mode register 2 (pm2). when used as an input port, use of an on- chip pull-up resistor can be specified by setting pull-up resistor opti on register b2 (pub2) in 1-bit units. (2) control mode in this mode, p20 to p26 function as the buzzer output, timer output, seri al interface data i/o, and serial clock i/o. (a) buzzer output this is the buzzer output pin of 16-bit timer 90. (b) to90 this is the timer output pin of 16-bit timer 90. (c) si20, so20 these are the serial data i/o pins of the serial interface. (d) sck20 this is the serial clock i/o pin of the serial interface. (e) rxd20, txd20 these are the serial data i/o pins of the asynchronous serial interface.
chapter 2 pin functions user?s manual u15075ej2v1ud 41 (f) asck20 this is the serial clock input pin of the asynchronous serial interface. caution when using p20 to p26 as serial interface pins, the i/o mode and out put latch must be set according to the functions to be used. for the de tails of the setting, refer to table 12-2 settings of serial interface 20 operating mode. 2.2.4 p30 to p33 (port 3) these pins constitute a 4-bit i/o port. in addition, they also function as timer i/o and external interrupt input. port 3 can be specified in the fo llowing operation mode in 1-bit units. (1) port mode in this mode, p30 to p33 functions as a 4-bit i/o port. port 3 can be set in the i nput or output port mode in 1- bit units by port mode register 3 (pm3). when used as an input port, use of an on- chip pull-up resistor can be specified by setting pull-up resistor opti on register b3 (pub3) in 1-bit units. (2) control mode in this mode, p30 to p33 function as timer i/o and external interrupt input. (a) tmi60 this is the external clock input pin to timer 60. (b) to50, to60, to61 these are the timer output pins of timer 50 and timer 60 (c) cpt90 this is the capture edge input pin of 16-bit timer 90. (d) intp0 to intp3 these are external interrupt input pins for whic h valid edges (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.5 p50 to p53 (port 5) these pins function as a 4-bit n-ch open-drain i/o port. port 5 can be set in the input or output port mode in 1-bit units by port mode register 5 (pm5). in the mask rom vers ion, use of an on-chip pull-up resistor can be specified by a mask option. 2.2.6 p60 to p65 (port 6) this is a 6-bit input-only port. in addition to a general-pur pose input port function, it has an a/d converter input function. (1) port mode in this mode, p60 to p65 function as 6-bit input-only port. (2) control mode in this mode, p60 to p65 function as analog inputs (ani0 to ani5) of a/d converter.
chapter 2 pin functions 42 user?s manual u15075ej2v1ud 2.2.7 p70 to p72 (port 7) these pins constitute a 3-bit i/o port. port 7 can be set in the input or output mode in 1-bit units by port mode register 7 (pm7). when used as an input port, use of an on-chip pull-up resist or can be specified by setting pull-up resistor option register b7 (pub7) in port units. 2.2.8 p80, p81 (port 8) note these pins constitute a 2-bit i/o port. port 8 can be set in the input or output mode in 1-bit units by port mode register 8 (pm8). when used as an input port, use of an on-chip pull-up resist or can be specified by setting pull-up resistor option register b8 (pub8) in port units. note only the pd789426 and pd789436 subseries. 2.2.9 p90 to p97 (port 9) note these pins constitute an 8-bit i/o port. port 9 can be set in the input or output mode in 1-bit units by port mode register 9 (pm9). when used as an input port, use of an on-chip pull-up resist or can be specified by setting pull-up resistor option register b9 (pub9) in port units. note only the pd789426 and pd789436 subseries. 2.2.10 s0 to s14 note these pins are segment signal output pins for the lcd controller/driver. note s0 to s4 in the case of the pd789426 and 789436 subseries 2.2.11 com0 to com3 these pins are common signal output pi ns for the lcd controller/driver. 2.2.12 v lc0 to v lc2 these pins are power supply vo ltage pins to drive the lcd. 2.2.13 caph, capl these pins are capacitor connec tion pins to drive the lcd. 2.2.14 reset this pin inputs an active-low system reset signal. 2.2.15 x1, x2 these pins are used to connect a crystal re sonator for main system clock oscillation. to supply an external clock, input the clo ck to x1 and input the inverted signal to x2. 2.2.16 cl1, cl2 (in case of rc oscillation (mask option) only) these pins are used to connect a resistor (r) and a c apacitor (c) for main system clock oscillation when rc oscillation (mask option) is selected. when supplying an external clock, input the clock to cl1 and leave cl2 open.
chapter 2 pin functions user?s manual u15075ej2v1ud 43 2.2.17 xt1, xt2 these pins are used to connect a crystal re sonator for subsystem clock oscillation. to supply an external clock, input the clock to xt1 and input the inverted signal to xt2. 2.2.18 v dd this is the positive power supply pin. 2.2.19 v ss this is the ground pin. 2.2.20 v pp ( pd78f9436, 78f9456 only) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. connect this pin in either of the following ways. ? independently connect to a 10 k ? pull-down resistor. ? by using a jumper on the board, c onnect directly to the dedicated flash programmer in the programming mode or to v ss in the normal operation mode. 2.2.21 ic (mask rom version only) the ic (internally connected) pin is used to set the pd789426, 789436, 789446, and 789456 subseries in the test mode before shipment. in the normal operat ion mode, directly connect this pin to the v ss pin with as short a wiring length as possible. if a potential difference is gener ated between the ic pin and v ss pin due to a long wiring length, or an external noise superimposed on the ic pin, the user program may not run correctly. ? directly connect the ic pin to the v ss pin. v ss ic keep short
chapter 2 pin functions 44 user?s manual u15075ej2v1ud 2.3 pin input/output circuits and r ecommended connection of unused pins the input/output circuit type of eac h pin and recommended connection of unused pi ns are shown in table 2-1. for the input/output circuit configurat ion of each type, see figure 2-1. table 2-1. types of pin input/output circuits pin name i/o circuit type i/o recommended connection of unused pins p00/kr0 to p03/kr3 8-a p10, p11 5-a p20 p21/bzo90 p22/ss20 p23/sck20/asck20 p24/so20/txd20 p25/si20/rxd20 p26/to90 input: independently connect to v dd or v ss via a resistor. output: leave open. p30/inpt0/cpt90 p31/inpt1/to50/tmi60 p32/inpt2/to60 p33/inpt3/to61 8-a input: independently connect to v ss via a resistor. output: leave open. p50 to p53 (mask rom version) 13-w p50 to p53 (flash memory version) 13-v i/o input: connect directly to v ss . output: leave this pin open at low-level output after clearing the output latch of the port to 0. p60/ani0 to p65/ani5 9-c input connect directly to v dd or v ss . p70 to p72 p80, p81 note 1 p90 to p97 note 1 5-a i/o input: independently connect to v dd or v ss via a resistor. output: leave open. s0 to s4 note 1 s0 to s14 note 2 17 output com0 to com3 18 v lc0 to v lc2 caph, capl ? leave open. xt1 input connect directly to v ss . xt2 leave open. av ss connect directly to v ss . av dd ? ? connect directly to v dd . reset 2 input ? ic connect directly to v ss . v pp ? ? independently connect a 10 k ? pull-down resistor, or connect directly to v ss . notes 1. when using the pd789426 and 789436 subseries 2. when using the pd789446 and 789456 subseries
chapter 2 pin functions user?s manual u15075ej2v1ud 45 figure 2-1. pin input/output circuits type 2 type 13-v schmitt-triggered input with hysteresis characteristics in v ss output data output disable in/out n-ch middle-voltage input buffer input enable type 5-a type 13-w pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch v ss v ss output data output disable in/out v dd n-ch middle-voltage input buffer input enable pull-up resistor (mask option) type 8-a type 17 pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch v ss p-ch p-ch v lc0 v lc1 n-ch p-ch n-ch v lc2 seg data p-ch out n-ch n-ch type 9-c type 18 in comparator + v ref (threshold voltage) av ss p-ch n-ch input enable - com data out p-ch p-ch v lc0 v lc1 n-ch v lc2 p-ch n-ch n-ch p-ch n-ch n-ch p-ch
user?s manual u15075ej2v1ud 46 chapter 3 cpu architecture 3.1 memory space the pd789426, 789436, 789446, and 789456 subseries can access 64 kb of memory space. figures 3-1 through 3-6 show the memory maps. figure 3-1. memory map ( pd789425, 789435) special function registers 256 8 bits internal high-speed ram 512 8 bits lcd display ram 5 4 bits reserved reserved internal rom 12288 8 bits ffffh ff00h feffh fd00h fcffh fa00h f9ffh 0000h program memory space data memory space 2fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area fa05h fa04h 3000h 2fffh
chapter 3 cpu architecture user?s manual u15075ej2v1ud 47 figure 3-2. memory map ( pd789426, 789436) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 5 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa05h fa04h 4000h 3fffh
chapter 3 cpu architecture user?s manual u15075ej2v1ud 48 figure 3-3. memory map ( pd78f9436) special function registers 256 8 bits internal high-speed ram 512 8 bits flash memory 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 5 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa05h fa04h 4000h 3fffh
chapter 3 cpu architecture user?s manual u15075ej2v1ud 49 figure 3-4. memory map ( pd789445, 789455) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 12288 8 bits ffffh ff00h feffh 0000h program memory space data memory space 2fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa0fh fa0eh 3000h 2fffh
chapter 3 cpu architecture user?s manual u15075ej2v1ud 50 figure 3-5. memory map ( pd789446, 789456) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa0fh fa0eh 4000h 3fffh
chapter 3 cpu architecture user?s manual u15075ej2v1ud 51 figure 3-6. memory map ( pd78f9456) special function registers 256 8 bits internal high-speed ram 512 8 bits flash memory 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa0fh fa0eh 4000h 3fffh
chapter 3 cpu architecture user?s manual u15075ej2v1ud 52 3.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the pd789426, 789436, 789446, and 789456 subserie s provide internal rom (or flash memory) with the following capacity for each product. table 3-1. internal rom capacity part number internal rom structure capacity pd789425, 789435, 789445, 789455 12288 8 bits pd789426, 789436, 789446, 789456 mask rom 16384 8 bits pd78f9436, 78f9456 flash memory 16384 8 bits the following areas are allocated to t he internal program memory space. (1) vector table area the 34-byte area of addresses 0000h to 0021h is reserved as a vector table area. this area stores program start addresses to be used when branching by the reset input or an interrupt request generation. of a 16- bit program address, the lower 8 bi ts are stored in an even address, and the higher 8 bits are stored in an odd address. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 0014h intwti 0004h intwdt 0016h inttm90 0006h intp0 0018h inttm50 0008h intp1 001ah inttm60 000ah intp2 001ch intad0 000ch intp3 001eh intwt 000eh intsr20/intcsi20 0020h intkr00 0012h intst20 (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh.
chapter 3 cpu architecture user?s manual u15075ej2v1ud 53 3.1.2 internal data memory (internal high-speed ram) space the pd789426, 789436, 789446, and 789456 subseries products incorporate the following ram. (1) internal high-speed ram internal high-speed ram is incorporat ed in the area between fd00h and feffh. the internal high-speed ram is also used as a stack. (2) lcd display ram lcd display ram is incorporated. the lcd display ram can also be used as ordinary ram. each subseries incorporates lcd di splay ram with the following capacity. table 3-3. lcd di splay ram capacity subseries name area capacity pd789426, 789436 subseries fa00h to fa04h 5 4 bits pd789446, 789456 subseries fa00h to fa0eh 15 4 bits 3.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allo cated in the area between ff00h to ffffh (see table 3-4 ).
chapter 3 cpu architecture user?s manual u15075ej2v1ud 54 3.1.4 data memory addressing the pd789426, 789436, 789446, and 789456 subserie s are provided with a variet y of addressing modes to make memory manipulation as efficient as possible. at the addresses corresponding to data memory area (fd00h to ffffh) especially, specific addressing modes that correspond to the particular function an ar ea, such as the special function registers are available. figures 3-7 through 3-12 show the data memory addressing modes. figure 3-7. data memory addressing ( pd789425, 789435) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 12288 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 5 4 bits reserved reserved fd00h fcffh fa00h f9ffh 3000h 2fffh fa05h fa04h
chapter 3 cpu architecture user?s manual u15075ej2v1ud 55 figure 3-8. data memory addressing ( pd789426, 789436) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 5 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa05h fa04h
chapter 3 cpu architecture user?s manual u15075ej2v1ud 56 figure 3-9. data memory addressing ( pd78f9436) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits flash memory 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 5 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa05h fa04h
chapter 3 cpu architecture user?s manual u15075ej2v1ud 57 figure 3-10. data memory addressing ( pd789445, 789455) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 12288 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh 3000h 2fffh fa0fh fa0eh
chapter 3 cpu architecture user?s manual u15075ej2v1ud 58 figure 3-11. data memory addressing ( pd789446, 789456) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa0fh fa0eh
chapter 3 cpu architecture user?s manual u15075ej2v1ud 59 figure 3-12. data memory addressing ( pd78f9456) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits flash memory 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 15 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa0fh fa0eh
chapter 3 cpu architecture user?s manual u15075ej2v1ud 60 3.2 processor registers the pd789426, 789436, 789446, and 789456 subserie s provide the following on-ch ip processor registers. 3.2.1 control registers the control registers contai n special functions to cont rol the program sequence status es and stack memory. the program counter, program status word, and stack pointer are c ontrol registers. (1) program counter (pc) the program counter is a 16-bit r egister that holds the address info rmation of the next program to be executed. in normal operation, the pc is automat ically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is execut ed, immediate data or r egister contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-13. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. the program status word contents are automatica lly stacked upon interrupt request generation or push psw instruction execution and ar e automatically restored upon exec ution of the reti and pop psw instructions. reset input sets psw to 02h. figure 3-14. program status word configuration 70 ie z 0 ac 0 0 1 cy psw
chapter 3 cpu architecture user?s manual u15075ej2v1ud 61 (a) interrupt enable flag (ie) this flag controls interrupt request a cknowledgement operati ons of the cpu. when 0, ie is set to the interrupt disable stat us (di), and interrupt reques ts other than non-maskable interrupt are all disabled. when 1, ie is set to the interrupt enable status (ei). interrupt request acknowledgement enable is controlled with an interrupt mask flag for various interrupt sources. ie is reset (0) upon di instruction execution or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0) in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (d) carry flag (cy) this flag stores overflow and underfl ow upon add/subtract instruction exec ution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
chapter 3 cpu architecture user?s manual u15075ej2v1ud 62 (3) stack pointer (sp) this is a 16-bit register to hold t he start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-15. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-16 and 3-17. caution since reset input makes the sp contents unde fined, be sure to initialize the sp before instruction execution. figure 3-16. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 higher register pairs figure 3-17. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs ret instruction pop rp instruction sp pc7 to pc0 higher register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3
chapter 3 cpu architecture user?s manual u15075ej2v1ud 63 3.2.2 general-purpose registers the general-purpose register s consist of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit r egister, or two 8-bit registers in pairs can be used as a 16-bit register (ax, bc, de, and hl). general-purpose registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, or hl) or absolute names (r0 to r7 and rp0 to rp3). figure 3-18. general-purpo se register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) function names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h
chapter 3 cpu architecture user?s manual u15075ej2v1ud 64 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special function register has a special function. the special function registers are allocat ed in the 256-byte area of ff00h to ffffh. special function registers can be m anipulated, like general-purpos e registers, by operat ion, transfer, and bit manipulation instructions. the manipul atable bit units (1, 8, and 16) differ depending on the special function register type. the manipulatable bits can be specified as follows. 1-bit manipulation describes a symbol reserved by the assembler for the 1-bit manipulation instructi on operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation describes a symbol reserved by the assembler for t he 8-bit manipulation instru ction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation describes a symbol reserved by the assembler fo r the 16-bit manipulation instruction operand. when addressing an address, describe an even address. table 3-4 lists the special function r egisters. the meanings of the symbol s in this table are as follows: symbol indicates the addresses of the implem ented special function registers. t he symbols shown in this column are the reserved words of the assembler, and have already been defined in the header file called ?sfrbit.h? of the c compiler. therefore, t hese symbols can be used as instruction oper ands if an assembler or integrated debugger is used. r/w indicates whether the special function r egister in question can be read or written. r/w: read/write r: read only w: write only bit manipulation unit indicates the bit units (1, 8, 16) in which the s pecial function register in question can be manipulated. after reset indicates the status of t he special function register w hen the reset signal is input.
chapter 3 cpu architecture user?s manual u15075ej2v1ud 65 table 3-4. special function register list (1/2) bit manipulation unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 ? ff01h port 1 p1 ? ff02h port 2 p2 ? ff03h port 3 p3 ? ff05h port 5 p5 r/w ? ff06h port 6 p6 r ? ff07h port 7 p7 ? ff08h port 8 note 1 p8 ? ff09h port 9 note 1 p9 r/w ? 00h ff0ch 8-bit compare register 60 cr60 ? ff0dh 8-bit compare register 50 cr50 cr6 note 2 w ? notes 3, 4 undefined ff0eh 8-bit timer counter 60 tm60 ? ff0fh 8-bit timer counter 50 tm50 tm6 note 2 r ? notes 3, 4 00h transmit shift register 20 txs20 w ? ? ffh ff10h receive buffer register 20 rxb20 sio20 r ? ? undefined ff14h ff15h a/d conversion result register 0 adcr0 note 5 r ? notes 3 0000h ff16h ff17h 16-bit compare register 90 cr90 note 2 w ? ? notes 3, 4 ffffh ff18h ff19h 16-bit timer counter 90 tm90 note 2 ? ? notes 3, 4 0000h ff1ah 16-bit capture register 90 ff1bh tcp90 note 2 r ? ? note 3 undefined ff20h port mode register 0 pm0 ? ff21h port mode register 1 pm1 ? ff22h port mode register 2 pm2 ? ff23h port mode register 3 pm3 ? ff25h port mode register 5 pm5 r/w ? ffh notes 1. pd789426 and 789436 subseries only. 2. name of sfr dedicated for 16-bit access. 3. only in short direct addressing, 16-bit access is possible. 4. these are 16-bit access dedicated r egisters, however, 8-bit access is possible. when performing 8-bit access, access using direct addressing. 5. when used as an 8-bit a/d converter ( pd789426 and 789446 subseries), only 8-bit access is possible. in this case, the address is ff15h. when used as a 10-bit a/d converter ( pd789436 and 789456 subseries), only 16-bit access is possible. when the pd78f9436, a flash memory version of the pd789425 or pd789426, is used, this register can be accessed in 8-bit units. however, only an object file assembled with the pd789425 or pd789426 can be used. the same is also true for the pd78f9456, a flash memory version of the pd789445 or pd789446: this register can be access ed in 8-bit units, but only an object file assembled with the pd789445 or pd789446 can be used.
chapter 3 cpu architecture user?s manual u15075ej2v1ud 66 table 3-4. special function register list (2/2) bit manipulation unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff27h port mode register 7 pm7 ? ff28h port mode register 8 note pm8 ? ff29h port mode register 9 note pm9 ? ffh ff32h pull-up resistor option register b2 pub2 ? ff33h pull-up resistor option register b3 pub3 ? ff37h pull-up resistor option register b7 pub7 ? ff38h pull-up resistor option register b8 note pub8 ? ff39h pull-up resistor option register b9 note pub9 ? ff42h watchdog timer clock select register wdcs ? ? ff48h 16-bit timer mode control register 90 tmc90 ? ff49h buzzer output control register 90 bzc90 ? ff4ah watch timer mode control register wtm r/w ? 00h ff4ch 8-bit compare register h60 crh60 w ? ? undefined ff4dh 8-bit timer mode control register 50 tmc50 ? ff4eh 8-bit timer mode control register 60 tmc60 r/w ? ff4fh carrier generator output control register 60 tca60 w ? ? ff70h asynchronous serial interface mode register 20 asim20 r/w ? ff71h asynchronous serial interface status register 20 asis20 r ? ff72h serial operation mode register 20 csim20 ? ff73h baud rate generator control register 20 brgc20 ? ? ff80h a/d converter mode register 0 adm0 ? ff84h analog input channel spec ification register 0 ads0 ? ffb0h lcd display mode register 0 lcdm0 ? ffb2h lcd clock control register 0 lcdc0 ? ffb3h lcd voltage amplification control register 0 lcdva0 ? ffe0h interrupt request flag register 0 if0 ? ffe1h interrupt request flag register 1 if1 ? 00h ffe4h interrupt mask flag register 0 mk0 ? ffe5h interrupt mask flag register 1 mk1 ? ffh ffech external interrupt mode register 0 intm0 ? ? ffedh external interrupt mode register 1 intm1 ? ? fff0h suboscillation mode register sckm ? fff2h subclock control register css ? fff5h key return mode register 00 krm00 ? fff7h pull-up resistor option register 0 pu0 ? fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization ti me select register osts ? ? 04h fffbh processor clock control register pcc r/w ? 02h note pd789426 and 789436 subseries only.
chapter 3 cpu architecture user?s manual u15075ej2v1ud 67 3.3 instruction address addressing an instruction address is determined by the program counter (p c) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an in struction to be fetched each time another instruction is ex ecuted. when a branch instruct ion is executed, the branch destination information is set to the pc and branched by the following addressing (f or details of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immedi ate data (displacement value: jdis p8) of an instruction code to the start address of the following instruction is transfe rred to the program counter (pc) and branched. the displacement value is treated as signed two?s comple ment data (?128 to +127) and bit 7 becomes a sign bit. this means that information is relatively branched to a location between ?128 and +127, from the start address of the next instruction when relative addressing is used. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates all bits 0. ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates all bits 1.
chapter 3 cpu architecture user?s manual u15075ej2v1ud 68 3.3.2 immediate addressing [function] immediate data in the instructi on word is transferred to the pr ogram counter (pc) and branched. this function is carried out when the call !addr 16 or br !addr16 instru ction is executed. call !addr16 and br !addr16 instruct ions can be branched to any location in the memory space. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr.
chapter 3 cpu architecture user?s manual u15075ej2v1ud 69 3.3.3 table indirect addressing [function] table contents (branch desti nation address) of the particular locati on to be addressed by the lower 5-bit immediate data of an instru ction code from bit 1 to bit 5 are trans ferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instructi on is executed. the in struction enables a branch to any location in the memory space by referring to t he addresses stored in the memo ry table at 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4?0 instruction code 3.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word ar e transferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 3 cpu architecture user?s manual u15075ej2v1ud 70 3.4 operand address addressing the following various methods are available to spec ify the register and memory (addressing) which undergo manipulation during inst ruction execution. 3.4.1 direct addressing [function] the memory indicated with imm ediate data in an instruction wo rd is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 0 0 1 0 1001op code 00000000 11111110 00h feh [illustration] 70 op code addr16 (lower) addr16 (higher) memory ? ? ? ? ?
chapter 3 cpu architecture user?s manual u15075ej2v1ud 71 3.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit dat a in an instruction word. the fixed space is the 256-byte space fe20h to ff1fh where the addressing is applied. internal high-speed ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addr essing is applied is a part of the whole sfr area. ports that are frequently accessed in a program and the compare register of the timer/event counter are mapped in this area, and these sf rs can be manipulated with a sma ll number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh i mmediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 1 1 1 10101 10010000 01010000 op code 90h (saddr-offset) 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1.
chapter 3 cpu architecture user?s manual u15075ej2v1ud 72 3.4.3 special function register (sfr) addressing [function] the memory-mapped special function registers (sfrs) are addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 256-byte space ff00h to ffffh. however, the sfrs mapped at ff00h to ff1fh can also be accessed with short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 11100111 00100000 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 3 cpu architecture user?s manual u15075ej2v1ud 73 3.4.4 register addressing [function] in the register addressing mode, general-purpose registers are access ed as operands. the general-purpose register to be accessed is specified by a register specification code or f unctional name in the instruction code. register addressing is carried out when an instruction with the following operand forma t is executed. when an 8-bit register is specified, one of the eight registers is specified wit h 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 0 0 1 0 1 0 00100101 register specification code incw de; when selecting the de register pair for rp instruction code 1 0001000 register specification code
chapter 3 cpu architecture user?s manual u15075ej2v1ud 74 3.4.5 register indirect addressing [function] in the register indirect addressing m ode, memory is manipulated according to the contents of a register pair specified as an operand. the r egister pair to be accessed is specified by the register pair s pecification code in an instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 00101011 [illustration] 15 0 8 d 7 e 0 7 7 0 a de addressed memory contents are transferred. memory address specified with register pair de.
chapter 3 cpu architecture user?s manual u15075ej2v1ud 75 3.4.6 based addressing [function] 8-bit immediate data is added to the cont ents of the base register, that is, t he hl register pair, and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 00101101 00010000 3.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatic ally employed when the push, po p, subroutine call, and return instructions are executed or t he register is saved/restored upon generation of an interrupt request. only the internal high-speed ram area can be addressed using stack addressing. [description example] in the case of push de instruction code 10101010
user?s manual u15075ej2v1ud 76 chapter 4 port functions 4.1 port functions the pd789426, 789436, 789446, and 789456 subserie s provide the ports shown in figures 4-1 and 4-2, enabling various methods of control. numerous other functions are provi ded that can be used in addition to the digital i/o port functions. for more information on these additional functions, see chapter 2 pin functions . figure 4-1. port types ( pd789426, 789436 subseries) p30 p33 p60 p00 p03 p10 p11 port 1 port 2 port 3 port 5 p20 p26 p65 port 0 port 6 p70 p72 port 8 port 7 p80 p81 p90 p97 port 9 p50 p53
chapter 4 port functions user?s manual u15075ej2v1ud 77 figure 4-2. port types ( pd789446, 789456 subseries) p30 p33 p60 p00 p03 p10 p11 port 1 port 2 port 3 p20 p26 p65 port 0 p70 p72 port 7 port 6 p50 p53 port 5
chapter 4 port functions user?s manual u15075ej2v1ud 78 table 4-1. port functions (1/2) pin name i/o function after reset alternate function p00 to p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by setti ng pull-up resistor option register 0 (pu0) or key return mode register 00 (krm00). input kr0 to kr3 p10, p11 i/o port 1. 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by setti ng pull-up resistor option register 0 (pu0). input ? p20 ? p21 bzo90 p22 ss20 p23 sck20/asck20 p24 so20/txd20 p25 si20/rxd20 p26 i/o port 2. 7-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by setti ng pull-up resistor option register b2 (pub2). input to90 p30 intp0/cpt90 p31 intp1/to50/tmi60 p32 intp2/to60 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by setti ng pull-up resistor option register b3 (pub3). input intp3/to61 p50 to p53 i/o port 5. 4-bit i/o port. input/output can be specified in 1-bit units. for a mask rom version, an on-chip pull-up resistor can be specified by a mask option. input ? p60 to p65 input port 6. 6-bit input port. input ani0 to ani5 p70 to p72 i/o port 7. 3-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by setti ng pull-up resistor option register b7 (pub7). input ?
chapter 4 port functions user?s manual u15075ej2v1ud 79 table 4-1. port functions (2/2) pin name i/o function after reset alternate function p80, p81 note i/o port 8. 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by setti ng pull-up resistor option register b8 (pub8). input ? p90 to p97 note i/o port 9. 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by setti ng pull-up resistor option register b9 (pub9). input ? note pd789426, 789436 subseries only 4.2 port configuration ports have the following har dware configuration. table 4-2. configuration of port item configuration control registers port mode register (pmm: m = 0 to 3, 5, 7 to 9) pull-up resistor option register (pu0, pub2, pub3, pub7 to pub9) pd789426, 789436 subseries total: 40 (cmos i/o: 30, cmos input: 6, n-ch open-drain i/o: 4) ports pd789446, 789456 subseries total: 30 (cmos i/o: 20, cmos input: 6, n-ch open-drain i/o: 4) pd789426, 789436 subseries total: 34 (software control: 30, mask option specification: 4) pull-up resistors pd789446, 789456 subseries total: 24 (software control: 20, mask option specification: 4)
chapter 4 port functions user?s manual u15075ej2v1ud 80 4.2.1 port 0 this is a 4-bit i/o port with an output latc h. port 0 can be specified in the i nput or output mode in 1-bit units by using the port mode register 0 (pm0). when the p00 to p03 pins are used as i nput port pins, on-chip pull-up resistors can be connected in 4-bit units by setting pu ll-up resistor option register 0 (pu0). port 0 is set in the input mode when the reset signal is input. figure 4-3 shows a block diagram of port 0. figure 4-3. block di agram of p00 to p03 wr krm00 v dd p00/kr0 to p03/kr3 wr puo rd wr port w rpm pu00 pm00 to pm03 krm000 p-ch internal bus selector output latch (p00 to p03) alternate function krm00: key return mode register 00 pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions user?s manual u15075ej2v1ud 81 4.2.2 port 1 this is a 2-bit i/o port with an output latc h. port 1 can be specified in the i nput or output mode in 1-bit units by using port mode register 1 (pm1). w hen using the p10 and p11 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units by setting pull- up resistor option register 0 (pu0). this port is set in the input mode when the reset signal is input. figure 4-4 shows a block diagram of port 1. figure 4-4. block diagram of p10 and p11 pu0: pull-up resistor option register 0 pm: port mode register rd: port 1 read signal wr: port 1 write signal wr pu0 rd wr port wr pm pu01 pm10, pm11 v dd p-ch p10, p11 internal bus selector output latch (p10, p11)
chapter 4 port functions user?s manual u15075ej2v1ud 82 4.2.3 port 2 this is a 7-bit i/o port with an output latc h. port 2 can be specified in the i nput or output mode in 1-bit units by using port mode register 2 (pm2). when using the p20 to p26 pins as input por t pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register b2 (pub2). the port is also used as the serial interface i/o, buzzer output, and timer output. this port is set in the input mode when the reset signal is input. figures 4-5 to 4-10 show block diagrams of port 2. caution when using the pins of port 2 as the seria l interface, the i/o or output latch must be set according to the function to be used. for how to set the latches, see figure 12-2 settings of serial interface 20 operating mode. figure 4-5. block diagram of p20 wr pub2 rd wr port wr pm pub20 output latch (p20) pm20 v dd p-ch p20 selector internal bus pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions user?s manual u15075ej2v1ud 83 figure 4-6. block diagram of p21 and p26 internal bus v dd p-ch p21/bzo90, p26/to90 wr pub2 rd wr port wr pm pub21, pub26 output latch (p21, p26) pm21, pm26 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions user?s manual u15075ej2v1ud 84 figure 4-7. block diagram of p22 internal bus v dd p-ch p22/ss20 wr pub2 rd wr port wr pm pub22 alternate function output latch (p22) pm22 selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions user?s manual u15075ej2v1ud 85 figure 4-8. block diagram of p23 internal bus v dd p-ch p23/asck20/ sck20 wr pub2 rd wr port wr pm pub23 alternate function output latch (p23) pm23 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions user?s manual u15075ej2v1ud 86 figure 4-9. block diagram of p24 pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal internal bus v dd p24/so20/txd20 wr pub2 rd wr port wr pm pub24 alternate function output latch (p24) pm24 selector p-ch ss20 output
chapter 4 port functions user?s manual u15075ej2v1ud 87 figure 4-10. block diagram of p25 p25/si20/ rxd20 wr pub2 rd wr port wr pm pub25 alternate function output latch (p25) pm25 v dd p-ch internal bus selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 4 port functions user?s manual u15075ej2v1ud 88 4.2.4 port 3 this is a 4-bit i/o port with an output latc h. port 3 can be specified in the i nput or output mode in 1-bit units by using port mode register 3 (pm3). when using the p30 to p33 pins as input por t pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register b3 (pub3). this port is also used as an external interrupt input, capture input, and timer i/o. this port is set in the input mode when the reset signal is input. figures 4-11 and 4-12 show block diagrams of port 3. figure 4-11. block diagram of p30 p30/intp0/cpt90 wr pub3 rd wr port wr pm pub30 pm30 v dd p-ch internal bus alternate function selector output latch (p30) pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 4 port functions user?s manual u15075ej2v1ud 89 figure 4-12. block di agram of p31 to p33 pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal p31/intp1/to50/ tmi60, p32/intp2/to60, p33/intp3/to61 wr pub3 rd wr port wr pm pub31 to pub33 pm31 to pm33 v dd p-ch internal bus alternate function selector output latch (p31 to p33) alternate function
chapter 4 port functions 90 user?s manual u15075ej2v1ud 4.2.5 port 5 this is a 4-bit n-ch open-drain i/o port wit h an output latch. port 5 can be spec ified in the input or output mode in 1-bit units by using port mode register 5 (pm5). for a mask rom version, use of an on- chip pull-up resistor can be specified by a mask option. this port is set in the input mode when the reset signal is input. figure 4-13 shows a block diagram of port 5. figure 4-13. block di agram of p50 to p53 internal bus selector rd pm50 to pm53 p50 to p53 n-ch wr port output latch (p50 to p53) wr pm v dd mask option resistor mask rom version only. for flash memory version, a pull-up resistor is not incorporated. pm: port mode register rd: port 5 read signal wr: port 5 write signal
chapter 4 port functions user?s manual u15075ej2v1ud 91 4.2.6 port 6 this is a 6-bit input-only port. this port is also used as the anal og input of an a/d converter. figure 4-14 shows a block diagram of port 6. figure 4-14. block diagram of port 6 v ref rd a/d converter p60/ani0 to p65/ani5 + ? internal bus
chapter 4 port functions 92 user?s manual u15075ej2v1ud 4.2.7 port 7 this is a 3-bit i/o port with an output latc h. port 7 can be specified in the i nput or output mode in 1-bit units by using port mode register 7 (pm7). when us ing the p70 to p72 pins as input por t pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register b7 (pub7). this port is set in the input mode when the reset signal is input. figure 4-15 shows a block diagram of port 7. figure 4-15. block diag ram of p70 to p72 wr pub7 rd wr port wr pm pub70 to pub72 output latch (p70 to p72) pm70 to pm72 v dd p-ch p70 to p72 internal bus selector pub7: pull-up resistor option register b7 pm: port mode register rd: port 7 read signal wr: port 7 write signal
chapter 4 port functions user?s manual u15075ej2v1ud 93 4.2.8 port 8 ( pd789426, 789436 subseries only) this is a 2-bit i/o port with an output latc h. port 8 can be specified in the i nput or output mode in 1-bit units by using port mode register 8 (pm8). when using pins p80 and p81 as input port pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register b8 (pub8). this port is set in the input mode when the reset signal is input. figure 4-16 shows a block diagram of port 8. figure 4-16. block diagram of p80 and p81 pub8: pull-up resistor option register b8 pm: port mode register rd: port 8 read signal wr: port 8 write signal wr pub8 rd wr port wr pm pub80, pub81 output latch (p80, p81) pm80, pm81 v dd p-ch p80, p81 internal bus selector
chapter 4 port functions 94 user?s manual u15075ej2v1ud 4.2.9 port 9 ( pd789426, 789436 subseries only) this is an 8-bit i/o port with an output latc h. port 9 can be specified in the i nput or output mode in 1-bit units by using port mode register 9 (pm9). when us ing the pins of this port as input por t pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register b9 (pub9). this port is set in the input mode when the reset signal is input. figure 4-17 shows a block diagram of port 9. figure 4-17. block diag ram of p90 to p97 wr pub9 rd wr port wr pm pub90 to pub97 output latch (p90 to p97) pm90 to pm97 v dd p-ch p90 to p97 internal bus selector pub9: pull-up resistor option register b9 pm: port mode register rd: port 9 read signal wr: port 9 write signal
chapter 4 port functions user?s manual u15075ej2v1ud 95 4.3 registers controlling port function the ports are controlled by the fo llowing two types of registers. ? port mode registers (pm0 to pm3, pm5, pm7 to pm9) ? pull-up resistor option registers (pu0, pub2, pub3, pub7 to pub9) (1) port mode registers (pm0 to pm3, pm5, pm7 to pm9) these registers are used to set por t input/output in 1-bit units. the port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch according to table 4-3. caution as port 3 has an alternate function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, th e interrupt mask flag should be preset to 1.
chapter 4 port functions 96 user?s manual u15075ej2v1ud figure 4-18. format of port mode register pmmn 0 output mode (output buffer on) input mode (output buffer off) 1 1 1 1 1 1 1 1 1 1 1 1 1 pm03 pm13 pm53 pm02 pm12 pm52 pm01 pm11 pm51 pm00 pm10 pm50 pm0 pm1 pm5 7 symbol address after reset 6543210 r/w ff20h ff21h ff25h ffh ffh ffh r/w r/w r/w 1 1 1 1 1 pm72 pm71 pm70 pm7 ff27h ffh r/w 1 1 1 1 1 1 pm81 pm80 pm8 note ff28h ffh r/w pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9 note ff29h ffh r/w 1 1 pm26 1 pm25 1 pm24 1 pm23 pm33 pm22 pm32 pm21 pm31 pm20 pm30 pm2 pm3 ff22h ff23h ffh ffh r/w r/w pmn pin input/output mode selection (m = 0 to 3, 5, 7 to 9, n = 0 to 7) note incorporated only in the pd789426 and 789436 subseries.
chapter 4 port functions user?s manual u15075ej2v1ud 97 table 4-3. port mode register and output latch settings when us ing alternate functions alternate function pin name name i/o pmxx pxx p00 to p03 kr0 to kr3 input 1 x p26 to90 output 0 0 intp0 input 1 x p30 cpt90 input 1 x intp1 input 1 x to50 output 0 0 p31 tmi60 input 1 x intp2 input 1 x p32 to60 output 0 0 intp3 input 1 x p33 to61 output 0 0 p60 to p65 ani0 to ani5 input 1 x caution when port 2 is used as a serial interface pin, the i/o latch or output latch must be set according to its function. for the setting method, see tabl e 12-2 settings of serial interface 20 operating mode. remark x: don?t care pmxx: port mode register pxx: port output latch (2) pull-up resistor option register 0 (pu0) pull-up resistor option register 0 (p u0) sets whether on-chip pull-up r egisters are used on ports 0 and 1 or not. on the port specified to use an on-ch ip pull-up resistor by pu0, the pu ll-up resistor can be internally used only for the bits set in the input mode. no on-chip pu ll-up resistors can be used for the bits set in the output mode regardless of the setting of pu0. this also applies to cases when the pins are used for alternate functions. pu0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pu0 to 00h. figure 4-19. format of pull-up resistor option register 0 pm on-chip pull-up resistor selection (m = 0, 1) 000000 pu01 pu00 pu0 address after reset r/w fff7h 00h r/w 765432<1><0> pu0m 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol caution bits 2 to 7 must be set to 0.
chapter 4 port functions 98 user?s manual u15075ej2v1ud (3) pull-up resistor option register b2 (pub2) pull-up resistor option register b2 (pub2) sets whether on-chip pull-up resistors on p20 to p26 are used or not. on the port specified to use an on-ch ip pull-up resistor by pub2, the pu ll-up resistor can be internally used only for the bits set in the input mode. no on-chip pu ll-up resistors can be used for the bits set in the output mode regardless of the setting of pub2. this also applies to cases when the pins are used for alternate functions. pub2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pub2 to 00h. figure 4-20. format of pull-up resistor option register b2 p2n on-chip pull-up resistor selection (n = 0 to 6) 0 pub26 pub25 pub24 pub23 pub22 pub21 pub20 pub2 address after reset r/w ff32h 00h r/w 7 <6> <5> <4> <3> <2> <1> <0> pub2n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol (4) pull-up resistor option register b3 (pub3) pull-up resistor option register b3 (pub3) sets whether on-chip pull-up resistors on p30 to p33 are used or not. on the port specified to use an on-ch ip pull-up resistor by pub3, the pu ll-up resistor can be internally used only for the bits set in the input mode. no on-chip pu ll-up resistors can be used for the bits set in the output mode regardless of the setting of pub3. this also applies to cases when the pins are used for alternate functions. pub3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pub3 to 00h. figure 4-21. format of pull-up resistor option register b3 p3n on-chip pull-up resistor selection (n = 0 to 3) 00 0 0 pub33 pub32 pub31 pub30 pub3 address after reset r/w ff33h 00h r/w 7654<3><2><1><0> pub3n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol
chapter 4 port functions user?s manual u15075ej2v1ud 99 (5) pull-up resistor option register b7 (pub7) pull-up resistor option register b7 (pub7) sets whether on-chip pull-up resistors on p70 to p72 are used or not. on the port specified to use an on-chip pull-up resi stor by pub7, the pull-up re sistor can be internally used only for bits set in the input mode. no on-chip pu ll-up resistors can be used for the bits set in the output mode regardless of the setting of pub7. this also applie s to when the pins are used for alternate function. pub7 is set with a 1-bit or 8-bit memory manipulation instructions. reset input sets pub7 to 00h. figure 4-22. format of pull-up resistor option register b7 p7n on-chip pull-up resistor selection (n = 0 to 2) 00 0 0 0 pub72 pub71 pub70 pub7 address after reset r/w ff37h 00h r/w 7 6 5 4 3 <2> <1> <0> pub7n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol (6) pull-up resistor option register b8 (pub8) note pull-up resistor option register b8 (pub8) sets whether on-chip pull-up resistors on p80 and p81 are used or not. on the port specified to use an on-chip pull-up resi stor by pub8, the pull-up re sistor can be internally used only for bits set in the input mode. no on-chip pu ll-up resistors can be used for the bits set in the output mode regardless of the setting of pub8. this also applie s to when the pins are used for alternate functions. pub8 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pub8 to 00h. note incorporated only in the pd789426 and 789436 subseries. figure 4-23. format of pull-up resistor option register b8 p8n on-chip pull-up resistor selection (n = 0, 1) 000000 pub81 pub80 pub8 address after reset r/w ff38h 00h r/w 765432<1><0> pub8n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol
chapter 4 port functions 100 user?s manual u15075ej2v1ud (7) pull-up resistor option register b9 (pub9) note pull-up resistor option register b9 (pub9) sets whether on-chip pull-up resistors on p90 to p97 are used or not. on the port specified to use an on-chip pull-up resi stor by pub9, the pull-up re sistor can be internally used only for bits set in the input mode. no on-chip pu ll-up resistors can be used for the bits set in the output mode regardless of the setting of pub9. this also applie s to when the pins are used for alternate function. pub9 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pub9 to 00h. note incorporated only in the pd789426 and 789436 subseries. figure 4-24. format of pull-up resistor option register b9 p9n on-chip pull-up resistor selection (n = 0 to 7) pub97 pub96 pub95 pub94 pub93 pub92 pub91 pub90 pub9 address after reset r/w ff39h 00h r/w <7> <6> <5> <4> <3> <2> <1> <0> pub9n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol
chapter 4 port functions user?s manual u15075ej2v1ud 101 4.4 port function operation the operation of a port differs depending on whether the port is set in the input or output m ode, as described below. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output la tch of a port by using a transfer inst ruction. the cont ents of the output latch can be output from the pins of the port. data once written to the output latch is retai ned until new data is writt en to the output latch. (2) in input mode a value can be written to the output latc h by using a transfer instruction. however, the status of the port pin is not changed because the out put buffer is off. data once written to the output latch is retai ned until new data is writt en to the output latch. caution a 1-bit memory manipulation instructi on is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 4.4.2 reading from i/o port (1) in output mode the status of an output latc h can be read by using a transfer instructi on. the contents of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 4.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed with the contents of the output latch. the re sult of the operation is written to the output latch. the contents of the out put latch are output from the port pins. data once written to the output latch is retai ned until new data is writt en to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instructi on is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined.
user?s manual u15075ej2v1ud 102 chapter 5 clock generator 5.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. a main system clock oscillator and a subsystem clock osc illator are available as the system clock oscillator. moreover, crystal/ceramic oscillation or rc oscillation c an be selected for the main system clock oscillator by a mask option. ? main system clock oscillator (crystal/ceramic oscillation) this circuit oscillates a frequency of 1.0 to 5.0 mh z. oscillation can be stopped by executing the stop instruction or setting the processo r clock control register (pcc). ? main system clock oscillator (rc oscillation) (mask option) this circuit oscillates a frequency of 2.0 to 4.0 mh z. oscillation can be stopped by executing the stop instruction or setting the processo r clock control register (pcc). ? subsystem clock oscillator this circuit oscillates a frequency of 32.768 khz. o scillation can be stopped by the suboscillation mode register (sckm). 5.2 clock generator configuration the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control registers processor cl ock control register (pcc) suboscillation mode register (sckm) subclock control register (css) oscillators main system clock oscillator subsystem clock oscillator
chapter 5 clock generator user?s manual u15075ej2v1ud 103 figure 5-1. block diag ram of clock generator f xt f x or f cc or prescaler f x 2 2 f cc 2 2 f xt 2 1/2 prescaler 16-bit timer 90 8-bit timer 60 watch timer lcd controller/driver clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller selector stop mcc pcc1 cls css0 internal bus suboscillation mode register (sckm) frc scc internal bus subclock control register (css) processor clock control register (pcc) subsystem clock oscillator x1 or cl1 x2 or cl2 xt1 xt2 main system clock oscillator
chapter 5 clock generator user?s manual u15075ej2v1ud 104 5.3 registers controlling clock generator the clock generator is controll ed by the following registers. ? processor clock control register (pcc) ? suboscillation mode register (sckm) ? subclock control register (css)
chapter 5 clock generator user?s manual u15075ej2v1ud 105 (1) processor clock control register (pcc) pcc sets cpu clock selection and the division ratio. pcc is set with a 1-bit or 8-bit me mory manipulation instruction. reset input sets pcc to 02h. figure 5-2. format of processo r clock control register control of main system clock oscillator operation mcc00000 pcc1 0 pcc symbol address after reset r/w fffbh 02h r/w <7>6543210 mcc 0 1 operation enabled operation disabled cpu clock (f cpu ) selection note at f x = 5.0 mhz operation, f xt = 32.768 khz operation at f cc = 4.0 mhz operation, f xt = 32.768 khz operation css0 0 0 1 1 pcc1 0 1 0 1 f x (0.2 s) f x /2 2 (0.8 s) f xt /2 (61 s) f cc (0.25 s) f cc /2 2 (1.0 s) note the cpu clock is selected according to a combinati on of the pcc1 flag in the processor clock control register (pcc) and the css0 flag in the s ubclock control register (css) (refer to 5.3 (3) subclock control register (css) ). cautions 1. bits 0 and 2 to 6 must be set to 0. 2. the mcc can be set only when the subsyst em clock has been select ed as the cpu clock. remarks 1. f x : main system clock oscillation frequency (crystal/ceramic oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation) 3. f xt : subsystem clock oscillation frequency cpu clock (f cpu ) 2 indicates the minimum instruction execut ion time. the following table shows minimum instruction execution time based on each setting value. minimum instruction execution time css0 pcc1 at f x = 5.0 mhz operation, f xt = 32.768 khz operation at f cc = 4.0 mhz operation, f xt = 32.768 khz operation 0 0 0.4 s 0.5 s 0 1 1.6 s 2.0 s 1 0 1 1 122 s
chapter 5 clock generator user?s manual u15075ej2v1ud 106 (2) suboscillation mode register (sckm) sckm selects a feedback resistor for the subsystem clock, and controls the o scillation of the clock. sckm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sckm to 00h. figure 5-3. format of subo scillation mode register feedback resistor selection note 000000frcscc sckm symbol address after reset r/w fff0h 00h r/w 76543210 frc 0 1 on-chip feedback resistor used on-chip feedback resistor not used control of subsystem clock oscillator operation scc 0 1 operation enabled operation disabled note the feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the supply voltage. only when the subclock is not used, the pow er consumption in stop mode can be further reduced by setting frc = 1. caution bits 2 to 7 must be set to 0.
chapter 5 clock generator user?s manual u15075ej2v1ud 107 (3) subclock control register (css) css specifies whether the main system or subsystem clock oscillator is to be selected. it also specifies the cpu clock operation status. css is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets css to 00h. figure 5-4. format of subclock control register cpu clock operation status 0 0 cls css0 0000 css address after reset r/w fff2h 00h r/w 76543210 cls 0 1 operation based on the output of the (divided) main system clock operation based on the subsystem clock selection of the main system or subsystem clock oscillator css0 0 1 (divided) output from the main system clock oscillator output from the subsystem clock oscillator symbol note note bit 5 is read only. caution bits 0 to 3, 6, and 7 must be set to 0.
chapter 5 clock generator user?s manual u15075ej2v1ud 108 5.4 system clock oscillators there are two types of system clock oscillators: the main system clock oscillator and the subsystem clock oscillator. the main system clock can be switched between crystal/ceramic oscillation and rc oscillation (mask option). 5.4.1 main system clock oscillato r (crystal/ceramic oscillation) the main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the x1 pin, and input the inverted signal to the x2 pin. figure 5-5 shows the external circuit of the main system clock oscillator (crystal/ceramic oscillation). figure 5-5. external circuit of main system clock oscillator (cryst al/ceramic oscillation) (a) crystal or ceramic osc illation (b) external clock crystal or ceramic resonator v ss x2 x1 external clock x1 x2 caution when using the main system or subsystem cl ock oscillator, wire as follo ws in the area enclosed by the broken lines in figures 5- 5 to 5-7 to avoid an adverse e ffect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator.
chapter 5 clock generator user?s manual u15075ej2v1ud 109 5.4.2 main system clock oscilla tor (rc oscillation) (mask option) this oscillator is oscillated by the resistor (r) and capacitor (c) (4.0 mhz typ. ) connected across the cl1 and cl2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the cl1 pin, and leave the cl2 pin open. figure 5-6 shows the external circuit of the main system clock oscillator (rc oscillation). figure 5-6. external circuit of main system clock oscillator (rc oscillation) (a) rc oscillation (b) external clock cl1 cr v ss cl2 external clock open cl1 cl2 5.4.3 subsystem clock oscillator the subsystem clock oscillator is oscillated by the cr ystal resonator (32.768 khz t yp.) connected across the xt1 and xt2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the xt1 pin, and input the inverted signal to the xt2 pin. figure 5-7 shows the external circuit of the subsystem clock oscillator. figure 5-7. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 v ss xt1 32.768 khz crystal resonator external clock xt1 xt2 caution when using the main system or subsystem cl ock oscillator, wire as follo ws in the area enclosed by the broken lines in figures 5- 5 to 5-7 to avoid an adverse e ffect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. when using the subsystem clock, particu lar care is required because the sub system clock oscillator is designed as a low-amplitude circuit for r educing current consumption.
chapter 5 clock generator user?s manual u15075ej2v1ud 110 5.4.4 example of incorr ect resonator connection figure 5-8 shows an example of incorrect connection fo r crystal/ceramic oscillation and figure 5-9 shows an example for rc oscillation. figure 5-8. examples of incorrect connect ion for crystal/ceram ic oscillation (1/2) (a) too long wiring (b) crossed signal line v ss x1 x2 v ss x1 x2 portn (n = 0 to 3, 5 to 9) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 high current v ss x1 ab c p mn v dd high current x2 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, re spectively, and connect a resistor to xt2 in series.
chapter 5 clock generator user?s manual u15075ej2v1ud 111 figure 5-8. examples of incorrect connect ion for crystal/ceram ic oscillation (2/2) (e) signal is fetched v ss x1 x2 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, re spectively, and connect a resistor to xt2 in series.
chapter 5 clock generator user?s manual u15075ej2v1ud 112 figure 5-9. examples of incorrect connection for rc oscillation (1/3) (a) too long wiring ? main system clock ? subsystem clock v ss cl2 cl1 xt1 xt2 v ss (b) crossed signal line ? main system clock ? subsystem clock v ss cl2 portn (n = 0 to 3, 5 to 9) cl1 portn (n = 0 to 3, 5 to 9) xt1 xt2 v ss
chapter 5 clock generator user?s manual u15075ej2v1ud 113 figure 5-9. examples of incorrect connection for rc oscillation (2/3) (c) wiring near high fluctuating current ? main system clock ? subsystem clock v ss cl2 cl1 high current xt1 xt2 v ss high current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) ? main system clock ? subsystem clock v ss v dd cl2 cl1 portn (n = 0 to 3, 5, 7 to 9) ab high current v dd portn (n = 0 to 3, 5, 7 to 9) xt1 xt2 v ss abc high current
chapter 5 clock generator user?s manual u15075ej2v1ud 114 figure 5-9. examples of incorrect connection for rc oscillation (3/3) (e) signal is fetched ? main system clock ? subsystem clock v ss cl2 cl1 xt1 xt2 v ss 5.4.5 divider circuit the divider circuit divides the output of the main system clock oscillator (f x , f cc ) to generate various clocks. 5.4.6 when no subsyst em clock is used if a subsystem clock is not necessary, for example, fo r low-power consumption oper ation or clock operation, handle the xt1 and xt2 pins as follows: xt1: connect to v ss xt2: leave open in this case, however, a small current leaks via the on- chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. to avoid this, set bit 1 (frc) of the suboscilla tion mode register (sckm) so that the on-chip feedback resistor will not be used. also in this case, handle the xt1 and xt2 pins as stated above.
chapter 5 clock generator user?s manual u15075ej2v1ud 115 5.5 clock generator operation the clock generator generates the following clocks and controls the operat ion modes of the cpu, such as the standby mode. ? main system clock f x or f cc ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the operation and function of the clock generator is dete rmined by the processor clock control register (pcc), suboscillation mode register (sckm), and subclo ck control register (css), as follows. (a) the low-speed mode 2f cpu of the main system clock is sele cted when the reset signal is generated (pcc = 02h). while a low level is input to the r eset pin, oscillation of the main system clock is stopped. (b) three types of cpu clocks f cpu (for details, see figure 5-2 format of pr ocessor clock control register ) can be selected by the pcc, sckm, and css settings. (c) two standby modes, stop and halt , can be used with the main system clock selected. in a system where no subsystem clock is used, setting bit 1 (f rc) of the sckm so t hat the on-chip feedback resistor cannot be used reduces pow er consumption in stop mode. in a system where a subsystem clock is used, setting sckm bit 0 to 1 can c ause the subsystem clock to stop oscillation. (d) css bit 4 (css0) can be used to select the subsyst em clock so that low cu rrent consumption operation is used (122 s: at 32.768 khz operation). (e) with the subsystem clock selected, it is possibl e to cause the main system clock to stop oscillating using bit 7 (mcc) of pcc. the halt mode can be used, but the stop mode cannot. (f) the clock pulse for the peripheral hardware is generated by dividing the fr equency of the main system clock, but the subsystem clock pulse is only supplied to the 16-bit timer, 8-bit timer, watch timer, and lcd controller/driver. the 16-bit timer, 8-bit timer, watch timer, and lcd contro ller/driver can therefore keep running even during standby. the other hardware stops when the main system clock stops because it runs based on the main system clock (e xcept for external input clock operations).
chapter 5 clock generator user?s manual u15075ej2v1ud 116 5.6 changing setting of s ystem clock and cpu clock 5.6.1 time required for switching between system clock and cpu clock the cpu clock can be selected by using bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css). actually, the specified clock is not selected immediately after the se tting of pcc has been changed, and the old clock is used for the duration of se veral instructions after that (see tables 5-2 and 5-3 ). table 5-2. maximum time required for switching cpu clock (when crystal/ceramic oscillation is selected) set value before switching set value after switching css0 pcc1 css0 pcc1 css0 pcc1 css0 pcc1 0 0 0 1 1 x 0 0 4 clocks 2f x /f xt clocks (306 clocks) 1 2 clocks f x /2f xt clocks (76 clocks) 1 x 2 clocks 2 clocks remarks 1. two clocks are the minimum instruction execut ion time of the cpu clock before switching. 2. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 3. x: don?t care table 5-3. maximum time required for switch ing cpu clock (when rc oscillation is selected) set value before switching set value after switching css0 pcc1 css0 pcc1 css0 pcc1 css0 pcc1 0 0 0 1 1 0 4 clocks 2f cc /f xt clocks (244 clocks) 0 1 2 clocks f cc /2f xt clocks (61 clocks) 1 2 clocks 2 clocks remarks 1. two clocks are the minimum instruction execut ion time of the cpu clock before switching. 2. the parenthesized values apply to operation at f cc = 4.0 mhz or f xt = 32.768 khz. 3. : don?t care
chapter 5 clock generator user?s manual u15075ej2v1ud 117 5.6.2 switching between system clock and cpu clock (1) when crystal/ceramic oscillation is selected the following describes switching between the system clock and cpu clock when crystal/ceramic oscillation is selected for the main system clock. figure 5-10. switching between system clock and cpu clock (crysta l/ceramic oscillation) system clock cpu clock interrupt request signal reset v dd f x f x f xt f x low-speed operation high-speed operation subsystem clock operation high-speed operation wait (6.55 ms: at 5.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on pow er application. the effect of resetting is released when the reset pin is later made high, and the main syst em clock starts oscillating. at this time, the oscillation stabilization time (2 15 /f x ) is automatically secured. after that, the cpu starts inst ruction execution at the slow s peed of the main system clock (1.6 s: at 5.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at high speed has elapsed, bit 1 (pcc1) of the processor clock cont rol register (pcc) and bit 4 (css0) of the subclock control register (css) are rewritten so that high-speed operat ion can be selected. <3> a drop of the v dd voltage is detected with an in terrupt request signal. the clock is switched to the subsystem clock (at this moment, the subsystem clo ck must be in the oscillati on stabilization status). <4> a recover of the v dd voltage is detected with an inte rrupt request signal. bit 7 (mcc) of pcc is set to 0, and then the main system clock starts oscillating. after the time required for the oscillation to stabilize has elapsed, pcc1 and css0 are rewritten so t hat high-speed operation can be selected again. caution when the main system clock is stoppe d and the device is operating on the subsystem clock, wait until the oscillation stabilization ti me has been secured by the program before switching back to the main system clock.
chapter 5 clock generator user?s manual u15075ej2v1ud 118 (2) when rc oscillation is selected the following describes switching between the system clock and cpu clock when rc oscillation is selected for the main system clock. figure 5-11. switching between system clock and cpu clock (rc oscillation) system clock cpu clock interrupt request signal reset v dd f cc f cc f xt f cc low-speed operation high-speed operation subsystem clock operation high-speed operation wait (32 s: at 4.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on pow er application. the effect of resetting is released when the reset pin is later made high, and the main syst em clock starts oscillating. at this time, the oscillation stabilization time (2 7 /f cc ) is automatically secured. after that, the cpu starts inst ruction execution at the slow s peed of the main system clock (2.0 s: at 4.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at high speed has elapsed, bit 1 (pcc1) of the processor clock cont rol register (pcc) and bit 4 (css0) of the subclock control register (css) are rewritten so that high-speed operat ion can be selected. <3> a drop of the v dd voltage is detected with an in terrupt request signal. the clock is switched to the subsystem clock (at this moment, the subsystem clo ck must be in the oscillati on stabilization status). <4> a recover of the v dd voltage is detected with an inte rrupt request signal. bit 7 (mcc) of pcc is set to 0, and then the main system clock starts oscillating. after the time required for the oscillation to stabilize has elapsed, pcc1 and css0 are rewritten so t hat high-speed operation can be selected again. caution when the main system clock is stoppe d and the device is operating on the subsystem clock, wait until the oscillation stabilization ti me has been secured by the program before switching back to the main system clock.
user?s manual u15075ej2v1ud 119 chapter 6 16-bit timer 90 6.1 16-bit timer 90 functions 16-bit timer 90 has the following functions. ? timer interrupt ? timer output ? buzzer output ? count value capture (1) timer interrupt an interrupt is generated when a count value and compare value matches. (2) timer output timer output can be controlled when a c ount value and compare value matches. (3) buzzer output buzzer output can be controlled by software. (4) count value capture a count value of 16-bit timer counter 90 (tm90) is latched into a capt ure register synchronizing with the capture trigger and retained.
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 120 6.2 16-bit timer 90 configuration 16-bit timer 90 includes the following hardware. table 6-1. 16-bit timer 90 configuration item configuration timer counters 16 bits 1 (tm90) registers compare register: 16 bits 1 (cr90) capture register: 16 bits 1 (tcp90) timer outputs 1 (to90) control registers 16-bit timer mode control register 90 (tmc90) buzzer output control register 90 (bzc90) port mode registers 2, 3 (pm2, pm3) port 2 (p2)
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 121 internal bus internal bus 16-bit timer mode control register 90 (tmc90) tof90 cpt900 cpt901 16-bit capture register 90 (tcp90) 16-bit counter read buffer 16-bit timer counter 90 (tm90) 16-bit compare register 90 (cr90) f x /2 2 f x /2 6 f x /2 7 f xt cpt90/intp0 /p30 toc90 tcl901 tcl900 toe90 f/f tod90 p26 output latch p21 output latch pm26 pm21 to90/p26 inttm90 bzo90/p21 match ovf buzzer output control register (bzc90) 3 bcs902 bcs901 bcs900 bzoe90 edge detector synchronization circuit f x write controller write controller f x /2 cpu clock selector selector selector figure 6-1. block diagram of 16-bit timer 90
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 122 (1) 16-bit compare register 90 (cr90) a value specified in cr90 is compar ed with the count in 16-bit timer count er 90 (tm90). if they match, an interrupt request (inttm90) is issued by cr90. cr90 is set with an 8-bit or 16-bit memory manipulati on instruction. any value from 0000h to ffffh can be set. reset input sets cr90 to ffffh. cautions 1. cr90 is designed to be manipulated with a 16-bit memory manipulation instruction. however, it can also be manipulated with an 8-bit memory manipulation instruction. when an 8-bit memory manipul ation instruction is used to set cr90, it must be accessed by direct addressing. 2. to overwrite cr90 during a count operation, it is necessary to disable interrupts in advance, using interrupt mask fl ag register 1 (mk1). it is also necessary to disable inversion of the timer output data, using 16-bi t timer mode control register 90 (tmc90). if the value in cr90 is rewritten in the inte rrupt-enabled state, an interrupt request may occur at the moment of rewrite. (2) 16-bit timer counter 90 (tm90) tm90 is used to count the number of pulses. the contents of tm90 are read with an 8-bit or 16-bit memory manipulation instruction. reset input sets tm90 to 0000h. cautions 1. the count becomes undefined when stop mode is deselected, because the count operation is performed befo re oscillation stabilizes. 2. tm90 is designed to be manipulated with a 16-bit memory manipulation instruction. however, it can also be manipulated with an 8-bit memory manipulation instruction. when an 8-bit memory instru ction is used to manipulate tm90, it must be accessed by direct addressing. 3. when an 8-bit memory ma nipulation instruction is used to manipulate tm90, the lower and higher bytes must be read as a pair, in this order. (3) 16-bit capture register 90 (tcp90) tcp90 captures the contents of tm90. it is set with an 8-bit or 16-bit memory manipulation instruction. reset input makes tcp90 undefined. caution tcp90 is designed to be manipulated wit h a 16-bit memory manipulation instruction. however, it can also be manipul ated with an 8-bit memory mani pulation instruction. when an 8-bit memory manipulation instruction is used to manipulate tcp90, it must be accessed by direct addressing. (4) 16-bit counter read buffer 90 this buffer is used to latch and hold the count value for tm90.
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 123 6.3 registers controlling 16-bit timer 90 16-bit timer 90 is controlled by the following four registers. ? 16-bit timer mode control register 90 (tmc90) ? buzzer output control register 90 (bzc90) ? port mode registers 2, 3 (pm2, pm3) ? port 2 (p2) (1) 16-bit timer mode control register 90 (tmc90) 16-bit timer mode control register 90 (tmc90) controls the setting of a count clock, capture edge, etc. tmc90 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc90 to 00h.
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 124 figure 6-2. format of 16-bit timer mode control register 90 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 symbol address after reset r/w ff48h 00h r/w note 5 <6> 4321<0> <7> tof90 0 1 overflow flag control reset or cleared by software set when the 16-bit timer overflows cpt901 0 0 1 1 capture edge selection cpt900 0 1 0 1 capture operation disabled captured at the rising edge of the cpt90 pin captured at the falling edge of the cpt90 pin captured at both the rising and falling edges of the cpt90 pin toc90 0 1 timer output data inversion control inversion disabled inversion enabled tcl901 0 0 1 1 16-bit timer counter 90 count clock selection tcl900 0 1 0 1 toe90 0 1 16-bit timer counter 90 output control output disabled (port mode) output enabled tod90 0 1 timer output data timer output data is "0" timer output data is "1" f x /2 2 (1.25 mhz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f xt (32.768 khz) note bit 7 is read-only. caution disable interrupts in advan ce by using the interrupt mask flag register (mk1) to change the data of tcl901 and tcl900. also, prevent th e timer output data fr om being inverted by setting toc90 to 0. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 125 (2) buzzer output control register 90 (bzc90) this register selects a buzzer frequency based on fcl se lected with the count clo ck select bits (tcl901 and tcl900), and controls the out put of the square wave. bzc90 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets bzc90 to 00h. figure 6-3. format of buzzer output control register 90 bzoe90 buzzer port output control disables buzzer port output. enables buzzer port output. 0 1 0 0 0 0 bcs902 bcs901 bcs900 bzoe90 bzc90 symbol address after reset r/w ff49h 00h r/w 6 754 bcs902 bcs901 bcs900 buzzer frequency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 21 <0> fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 7 fcl = f xt fcl/2 4 (78.1 khz) fcl/2 5 (39.1 khz) fcl/2 8 (4.88 khz) fcl/2 9 (2.44 khz) fcl/2 10 (1.22 khz) fcl/2 11 (610 hz) fcl/2 12 (305 hz) fcl/2 13 (153 hz) fcl/2 4 (4.88 khz) fcl/2 5 (2.44 khz) fcl/2 8 (305 hz) fcl/2 9 (153 hz) fcl/2 10 (76 hz) fcl/2 11 (38 hz) fcl/2 12 (19 hz) fcl/2 13 (10 hz) fcl/2 4 (2.44 khz) fcl/2 5 (1.22 khz) fcl/2 8 (153 hz) fcl/2 9 (76 hz) fcl/2 10 (38 hz) fcl/2 11 (19 hz) fcl/2 12 (10 hz) fcl/2 13 (5 hz) fcl/2 4 (2.05 khz) fcl/2 5 (1.02 khz) fcl/2 8 (128 hz) fcl/2 9 (64 hz) fcl/2 10 (32 hz) fcl/2 11 (16 hz) fcl/2 12 (8 hz) fcl/2 13 (4 hz) note note bits 4 to 7 must be set to 0. caution if the subclock is selected as the count clock (tcl901 = 1, tc l900 = 1: see figure 6-2 format of 16-bit timer mode control register 90), the subclock is not synchronized when buzzer port output is enabled. in this case, the capture function and tm90 read function are disabled. in addition, the count value of tm90 is undefined. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 126 (3) port mode registers 2, 3 (pm2, pm3) pm2 and pm3 are used to set each bit of ports 2 and 3 to input or output. when the p26/to90 pin is used for timer output, rese t the output latch of p 26 and pm26 to 0; when pin p21/bzo90 is used for buzzer output, reset the output latch of p26 and pm26 to 0. when using the p30/intp0/cpt90 pin as a capture input, set pm30 to 1. pm2 and pm3 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input sets pm2 and pm3 to ffh. figure 6-4. format of port mode registers 2, 3 pmmn pmn pin i/o mode (mn = 20 to 26, 30 to 33) output mode (output buffer on) input mode (output buffer off) 0 1 1 1 1 1 pm33 pm32 pm31 pm30 pm3 symbol address after reset r/w ff23h ffh r/w 6 754 3 21 0 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 symbol address after reset r/w ff22h ffh r/w 6 754 3 21 0
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 127 6.4 16-bit timer 90 operation 6.4.1 operation as timer interrupt 16-bit timer 90 can generate interrupts repeatedly each time the free-running counter val ue reaches the value set to cr90. since this counter is not cleared and holds the count even after an inte rrupt is generated, the interval time is equal to one cycle of the count clock set in tcl901 and tcl900. to operate 16-bit timer 90 as a timer interrupt, the following settings are required. ? set count values in cr90 ? set 16-bit timer mode control register 90 (tmc90) as shown in figure 6-5. figure 6-5. settings of 16-bit timer mode cont rol register 90 for timer interrupt operation ? 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 setting of count clock (see table 6-2 ) caution if both the cpt901 and cpt900 flags are set to 0, the capture operation is prohibited. when the count value of 16-bit time r counter 90 (tm90) matches the va lue set in cr90, counting of tm90 continues and an interrupt request signal (inttm90) is generated. table 6-2 shows interval time, and figure 6-6 shows timing of timer interrupt operation. caution when rewriting the value in cr90 during a count operation, be sure to execute the following processing. <1> set interrupt disabled (set tmmk90 (bit 1 of interrupt mask flag register 1 (mk1)) to 1). <2> disable inversion control of ti mer output data (set toc90 to 0) if the value in cr90 is rewritten in the interrup t-enabled state, an interr upt request may occur at the moment of rewrite. table 6-2. interval time of 16-bit timer 90 tcl901 tcl900 count clock interval time 0 0 2 2 /f x (0.8 s) 2 18 /f x (52.4 ms) 0 1 2 6 /f x (12.8 s) 2 22 /f x (838.9 ms) 1 0 2 7 /f x (25.6 s) 2 23 /f x (1.68 s) 1 1 1/f xt (30.5 s) 2 16 /f xt (2.0 s) remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 128 figure 6-6. timing of timer interrupt operation cr90 tm90 count value count clock inttm90 to90 tof90 nn n nn t 0000h n ffffh n 0000h 0001h 0001h interrupt acknowledgment interrupt acknowledgment overflow flag set remark n = 0000h to ffffh
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 129 6.4.2 operation as timer output 16-bit timer 90 can invert the timer output repeatedly each time the free-running counter va lue reaches the value set to cr90. since this counter is not cleared and holds the count even after the timer output is inverted, the interval time is equal to one cycle of the count clock set in tcl901 and tcl900. to operate 16-bit timer 90 as a timer out put, the following settings are required. ? set p26 to output mode (pm26 = 0). ? reset output latch of p26 to 0. ? set the count value in cr90. ? set 16-bit timer mode control register 90 (tmc90) as shown in figure 6-7. figure 6-7. settings of 16-bit timer mode c ontrol register 90 for timer output operation ? 0/1 0/1 0/1 1 0/1 0/1 1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 setting of count clock (see table 6-2 ) inverse enable of timer output data to90 output enable caution if both the cpt901 flag and cpt900 flag ar e set to 0, the capture operation is prohibited. when the count value of 16-bit timer c ounter 90 (tm90) matches the value set in cr90, the output status of the to90/p26 pin is inverted. this enables timer output. at that time, tm90 counting c ontinues and an interrupt request signal (inttm90) is generated. figure 6-8 shows the timing of time r output (see table 6-2 for the inte rval time of the 16-bit timer). figure 6-8. timer output timing cr90 tm90 count value count clock inttm90 tof90 nn n nn t 0000h n ffffh n 0000h 0001h 0001h to90 note interrupt acknowledgment interrupt acknowledgment overflow flag set note the initial value of to90 becomes lo w level when output is enabled (toe90 = 1). remark n = 0000h to ffffh
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 130 6.4.3 capture operation the capture operation cons ists of latching the count value of 16-bit time r register 90 (tm90) in to a capture register in synchronization with a capture tri gger, and retaining the count value. set tmc90 as shown in figure 6-9 to allow 16- bit timer 90 to start the capture operation. figure 6-9. settings of 16-bit timer mode control register 90 for capture operation ? 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 count clock selection capture edge selection (see table 6-3 ) 16-bit capture register 90 (tcp90) st arts a capture operation after a cpt 90 capture trigger edge is detected, and latches and retains the count value of 16-bit timer register 90. the tcp90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection. table 6-3 and figure 6-10 show the se ttings of the capture edge and the capt ure operation timing, respectively. table 6-3. settings of capture edge cpt901 cpt900 capture edge selection 0 0 capture operation prohibited 0 1 cpt90 pin rising edge 1 0 cpt90 pin falling edge 1 1 cpt90 pin both edges caution because tcp90 is rewritten when a capture tr igger edge is detected during tcp90 read, disable the capture trigger edge de tection during tcp90 read. figure 6-10. capture operation timing (b oth edges of cpt90 pin are specified) count clock tm90 count read buffer tcp90 cpt90 0000h 0000h 0001h 0001h undefined n n n m 1 m m m capture start capture start capture edge detection capture edge detection
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 131 6.4.4 16-bit timer counter 90 readout the count value of 16-bit timer c ounter 90 (tm90) is read out using a 16-bit manipulation instruction. tm90 readout is performed through a counter read buffer. the counter read bu ffer latches the tm90 count value, and the buffer operation is held pending at the cpu clock fa lling edge after the read signal of the tm90 lower byte rises, and the count value is retained. the retained counter read buffer val ue can be read out as the count value. cancellation of the pending state is performed at the cpu clock falling edge after the read signal of the tm90 higher byte falls. reset input sets tm90 to 0000h and tm90 starts free-running. figure 6-11 shows the timing of 16-bit timer counter 90 readout. cautions 1. the count value after releasing st op becomes undefined because the count operation is executed during the oscillation stabilization time. 2. though tm90 is designed for a 16-bit transfer in struction, an 8-bit tr ansfer instruction can also be used. when using an 8-bit transfer instru ction, execute it by direct addressing. 3. when using an 8-bit transfer instruction, execute in the order from lower byte to higher byte in pairs. if only the lower byte is read, th e pending state of the counter read buffer is not canceled, and if only the higher byte is read, an undefined c ount value is read. figure 6-11. 16-bit timer counter 90 readout timing cpu clock count clock tm90 count read buffer tm90 read signal 0000h 0000h 0001h 0001h n n n + 1 read signal latch prohibited period
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 132 6.4.5 buzzer output operation the buzzer frequency is set using buzzer output control register 90 (bzc90) based on the count clock selected with tcl901 and tcl900 of tmc90 (source clock). a s quare wave of the set buzzer frequency is output. table 6-4 shows the buzzer frequency. set 16-bit timer 90 as follows to use it for buzzer output: ? set p21 to output mode (pm21 = 0). ? reset output latch of p21 to 0. ? set a count clock using tcl901 and tcl900. ? set bzc90 as shown in figure 6-12. figure 6-12. settings of buzzer output cont rol register 90 for buzzer output operation 0 0 0 0 0/1 0/1 0/1 1 bcs902 bcs901 bcs900 bzoe90 bzc90 setting of buzzer frequency (see table 6-4 ) enables buzzer output table 6-4. buzzer frequency of 16-bit timer 90 buzzer frequency bcs902 bcs901 bcs900 fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 7 fcl = f xt 0 0 0 fcl/2 4 (78.1 khz) fcl/2 4 (4.88 khz) fcl/2 4 (2.44 khz) fcl/2 4 (2.05 khz) 0 0 1 fcl/2 5 (39.1 khz) fcl/2 5 (2.44 khz) fcl/2 5 (1.22 khz) fcl/2 5 (1.02 khz) 0 1 0 fcl/2 8 (4.88 khz) fcl/2 8 (305 hz) fcl/2 8 (153 hz) fcl/2 8 (128 hz) 0 1 1 fcl/2 9 (2.44 khz) fcl/2 9 (153 hz) fcl/2 9 (76 hz) fcl/2 9 (64 hz) 1 0 0 fcl/2 10 (1.22 khz) fcl/2 10 (76 hz) fcl/2 10 (38 hz) fcl/2 10 (32 hz) 1 0 1 fcl/2 11 (610 hz) fcl/2 11 (38 hz) fcl/2 11 (19 hz) fcl/2 11 (16 hz) 1 1 0 fcl/2 12 (305 hz) fcl/2 12 (19 hz) fcl/2 12 (10 hz) fcl/2 12 (8 hz) 1 1 1 fcl/2 13 (153 hz) fcl/2 13 (10 hz) fcl/2 13 (5 hz) fcl/2 13 (4 hz) remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 133 6.5 notes on 16-bit timer 90 6.5.1 notes on using 16-bit timer 90 usable functions differ according to the settings of the count clock selection, cpu clock operation, system clock oscillation status, and bzoe90 (bit 0 of bu zzer output control register 90 (bzc90)). refer to the following table. system clock count clock cpu clock main system clock subsystem clock bzoe90 capture tm90 read buzzer output timer output timer interrupt oscillating note 1 note 2 main stopped oscillating/stopped oscillating note 2 f x /2 2 , f x /2 6 , f x /2 7 sub stopped oscillating 1/0 0 oscillating 1 oscillating stopped 1/0 0 oscillating 1 main stopped (stop mode) stopped 1/0 0 oscillating 1 0 f xt sub stopped oscillating 1 notes 1. tm90 is enabled only when the cpu clock is in high-speed mode. 2. output is enabled when bzoe90 = 1. cautions 1. the capture function uses f x /2 for control (refer to figure 6- 1 block diagram of 16-bit timer 90). therefore, the capture function cannot be used when the ma in system clock is stopped. 2. the read function of tm90 uses the cpu clock for control (ref er to figure 6-1), and reads an undefined value when the cpu clock is slow er than the count cl ock (values are not guaranteed). when reading tm90, set the c ount clock to the same speed as the cpu clock (when the cpu clock is the main system clock, high-speed mode is set), or select a clock slower than the cpu clock. 3. when the subsystem clock is selected as the count cl ock and bzoe90 is set to 0, the subsystem clock selected as the tm90 count clock is one that has been synchronized with the main system clock (refer to figure 6-1). therefore, when the main system clock oscillation is stopped, the ti mer operation is stopped because the clock supplied to the 16- bit timer is stopped (timer in terrupt is not generated). moreover, when the subsystem clock is selected as the count clock and bzoe90 is set to 1, the capture and tm90 read values are not gua ranteed because the sub system clock is not synchronized. therefore, be sure to set bzoe 90 to 0 when using the capture and tm90 read functions (when the subsystem clock is select ed as the count clock, buzzer output, capture, and tm90 read functions cannot be used at the same time).
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 134 make the following settings when stopping the main system clock oscillation to support low current consumption and releasing the halt mode. count clock: subsystem clock cpu clock: subsystem clock main system clock: oscillation stopped bzoe90: 1 (buzzer output enabled) at this time, when the setting of p21, the buzzer output alternate function pi n, is ?pm21 = 0, p21 = 0?, a square wave of the buzzer frequency is output from p21. to avoid outputting the buzzer frequency, make either of the following settings. ? set p21 to input mode (pm21 = 1) ? if p21 cannot be set to input mode, set the port latch val ue of p21 to 1 (p21 = 1) (in this case, a high level is output from p21)
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 135 6.5.2 restrictions on rewrit ing 16-bit compare register 90 (1) when rewriting the compare regi ster (cr90), be sure to disable interrupts (tmmk90 = 1), and disable inversion control of timer output (toc90 = 0) first. if cr90 is rewritten with interrupts enabled, an interr upt request may be generated at the point of rewrite. (2) the interval time may be double the intended time depending on the timing at whic h the compare register (cr90) is rewritten. likewise, the timer output waveform may be shorter or double the intended output. to avoid this, rewrite usi ng one of the following procedures. rewriting by 8-bit access <1> disable interrupts (tmmk90 = 1), and disable in version control of timer output (toc90 = 0) <2> rewrite the higher byte of cr90 (16 bits) first <3> next, rewrite the lower byte of cr90 (16 bits) <4> clear the interrupt request flag (tmif90) <5> after more than half the cycle of the count clock has passed from the start of the interrupt, enable timer interrupts and timer output inversion (when count clock = 64/f x , cpu clock = f x ) tm90_vct: set1 tmmk90 ;timer interrupt disable (6 clocks) clr1 tmc90.3 ;timer output inversion disable (6 clocks) mov a,#xxh ;higher byte rewrite value setting (6 clocks) mov !0ff17h,a ;cr90 higher byte rewriting (8 clocks) mov a,#yyh ;lower byte rewrite value setting (6 clocks) mov !0ff16h,a ;cr90 lower byte rewriting (8 clocks) clr1 tmif90 ;interrupt request flag clearing (6 clocks) clr1 tmmk90 ;timer interrupt enable (6 clocks) set1 tmc90.3 ;timer output inversion enable note this is because the inttm90 signal is set to the high level for a period of half the cycle of the count clock after an interrupt is generated, so the output will be inverted if toc90 is set to 1 during this period. more than 32 clocks in total note
chapter 6 16-bit timer 90 user?s manual u15075ej2v1ud 136 rewriting by 16-bit access <1> disable interrupts (tmmk90 = 1), and disable in version control of timer output (toc90 = 0) <2> rewrite cr90 (16 bits) <3> wait for more than one cycle of the count clock <4> clear the interrupt request flag (tmif90) <5> enable timer interrupts and timer output inversion (when count clock = 64/f x , cpu clock = f x ) tm90_vct: set1 tmmk90 ;timer interrupt disable clr1 tmc90.3 ;timer output inversion disable movw ax,#xxyyh ;cr90 rewrite value setting movw cr90,ax ;cr90 rewriting nop nop : nop nop clr1 tmif90 ;interrupt request flag clearing clr1 tmmk90 ;timer interrupt enable set1 tmc90.3 ;timer output inversion enable note wait for more than one cycle of the count clock a fter the instruction rewrit ing cr90 (movw cr90, ax) before clearing the interr upt request flag (tmif90). 32 nop (wait for 64/f x ) note
user?s manual u15075ej2v1ud 137 chapter 7 8-bit timers 50, 60 7.1 8-bit timers 50, 60 functions an 8-bit timer (one channel, timer 50) and an 8-bit timer/ev ent counter (one channel, time r 60) are incorporated in the pd789426, 789436, 799446, 789456 subserie s. the operation modes listed in the following table can be set via mode register settings. table 7-1. operation modes channel mode timer 50 timer 60 8-bit timer counter mode (discrete mode) available available 16-bit timer counter mode (cascade connection mode) available carrier generator mode available pwm output mode available (free-running mode) available (pulse generator mode) (1) 8-bit timer counter mode (discrete mode) the following functions can be used in this mode. ? interval timer with 8-bit resolution ? external event counter with 8- bit resolution (timer 40 only) ? square wave output with 8-bit resolution (2) 16-bit timer counter m ode (cascade connection mode) operation as a 16-bit time r/event counter is enabled dur ing cascade connection mode. the following functions can be used in this mode. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square wave output with 16-bit resolution (3) carrier generator mode the carrier clock generated by timer 60 is output in cycles set by timer 50. (4) pwm output mode (a) timer 50: free-running mode the timer output status in verts repeatedly due to a match between tm50 and cr50 and tm50 overflow, and pulses of any duty ratio are output.
chapter 7 8-bit timers 50, 60 138 user?s manual u15075ej2v1ud (b) timer 60: pulse generator mode the timer output status invert s repeatedly due to the settings of tm60, cr60, and crh60, and pulses of any duty ratio are output (eit her p32/intp2/to60 or p33/intp3/ to61 can be selected as the timer output pin using software). 7.2 8-bit timers 50, 60 configuration 8-bit timers 50 and 60 include the following hardware. table 7-2. 8-bit timer configuration item configuration timer counters 8 bits 2 (tm50, tm60) registers compare registers: 8 bits 3 (cr50, cr60, crh60) timer outputs 3 (to50, to60, to61) control registers 8-bit timer mode control register 50 (tmc50) 8-bit timer mode control register 60 (tmc60) carrier generator output control register 60 (tca60) port mode register 3 (pm3) port 3 (p3)
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 139 teg50 tcl500 tcl501 8-bit timer mode control register 50 (tmc50) decoder selector 8-bit compare register 50 (cr50) 8-bit timer counter 50 (tm50) from figure 7-2 (e) timer 60 match signal (in cascade connection mode) from figure 7-2 (d) count operation start signal (in cascade connection mode) inttm50 f x /2 3 f x /2 7 timer 60 interrupt request signal (from figure 7-2 (b)) carrier clock (in carrier generator mode) or timer 60 output signal (in a mode other than carrier generator mode) (from figure 7-2 (c)) cascade connection mode match internal bus ovf bit 7 of tm60 (from figure 7-2 (a)) toe50 p31 output latch pm31 to figure 7-2 (f) timer 50 match signal (in cascade connection mode) to50/tmi60/intp1/p31 tce50 tcl502 f x f xt tmd500 tmd501 s q in r q ck clear pwm mode to figure 7-2 (g) timer 50 match signal (in carrier generator mode) selector selector figure 7-1. block diagram of timer 50
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 140 tce60 tcl602 tcl601 tcl600 tmd601 tmd600 toe60 8-bit timer mode control register 60 (tmc60) decoder 8-bit timer counter 60 (tm60) f/f clear 8-bit compare register 60 (cr60) selector output control ler note inttm60 match reset pwm mode cascade connection mode 8-bit compare register h60 (crh60) internal bus ovf f x f x /2 2 tmi60/to50 /intp1/p31 f tmi /2 f tmi /2 2 f tmi /2 3 to60/intp2/p32 f tmi rmc60 nrzb60 nrz60 carrier generator output control register 60 (tca60) to61/intp3/p33 prescaler selector count operation start signal to timer 50 (in cascade connection mode) to figure 7-1 (d) tm50 match signal (in cascade connection mode) tm60 timer counter match signal (in cascade connection mode) from figure 7-1 (f) to figure 7-1 (e) count clock input signal to tm50 to figure 7-1 (a) bit 7 of tm60 (in cascade connection mode) to figure 7-1 (c) carrier clock (during carrier generator mode) or timer 60 output signal (in a mode other than carrier generator mode) to figure 7-1 (b) timer 60 interrupt request signal from figure 7-1 (g) timer counter match signal from timer 50 (in carrier generator mode) figure 7-2. block diagram of timer 60 note for details, see figure 7-3 .
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 141 figure 7-3. block diagram of output controller (timer 60) f/f pm32 p32 output latch to60/p32/ intp2 toe60 toe61 p33 output latch pm33 to61/p33/ intp3 timer 60 output signal (1) 8-bit compare register 50 (cr50) this 8-bit register is used to continually compare t he value set to cr50 with the count value in 8-bit timer counter 50 (tm50) and to generate an interrupt request (inttm50) when a match occurs. cr50 is set with an 8-bit memory manipulation instruction. reset input makes cr50 undefined. cautions 1. if the cr50 is overwritten during ti mer operation in the pwm output mode (tmd501 = 1, tmd500 = 0), a high level may be output for 1 cycle immediately after. if this waveform poses a problem for the appli cation, either <1> stop the timer when overwriting the cr50, or <2> overwrite the cr50 with the toe50 in a cleared status. 2. if the valid edge of the count clock is selected for both edges in the pwm output mode (teg50 = 1), do not set 00h, 01h, and ffh to the cr50. if the rising edge is selected (teg50 = 0), do not set 00h to cr50. (2) 8-bit compare register 60 (cr60) this 8-bit register is used to continually compare t he value set to cr60 with the count value in 8-bit timer counter 60 (tm60) and to generate an interrupt request (inttm60) when a match occurs. when connected to tm50 via a cascade connection and used as a 16-bit ti mer/event counter, the in terrupt request (inttm60) occurs only when matches occur simultaneous ly between cr50 and tm50 and between cr60 and tm60 (inttm50 does not occur). cr60 is set with an 8-bit memory manipulation instruction. reset input makes cr60 undefined. (3) 8-bit compare register h60 (crh60) in pwm output mode, the high-level width of time r output is set by writing a value to crh60. crh60 is set with an 8-bit memory manipulation instruction. reset input makes crh60 undefined.
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 142 (4) 8-bit timer counters 50 and 60 (tm50 and tm60) these are 8-bit registers that ar e used to count the count pulse. tm50 and tm60 are read with an 8-bit me mory manipulation instruction. reset input sets tm50 and tm60 to 00h. tm50 and tm60 are cleared to 00h under the following conditions. (a) discrete mode (i) tm50 ? after reset ? when tce50 (bit 7 of 8-bit timer mode c ontrol register 50 (tmc50)) is cleared to 0 ? when a match occurs between tm50 and cr50 ? when the tm50 count value overflows (ii) tm60 ? after reset ? when tce60 (bit 7 of 8-bit timer mode c ontrol register 60 (tmc60)) is cleared to 0 ? when a match occurs between tm60 and cr60 ? when the tm60 count value overflows (b) cascade connection mode (tm50 and tm 60 are simultaneously cleared to 00h) ? after reset ? when the tce60 flag is cleared to 0 ? when matches occur simultaneously bet ween tm50 and cr50 and between tm60 and cr60 ? when the tm50 and tm60 count va lues overflow simultaneously (c) carrier generator mode (i) tm50 ? after reset ? when the tce50 flag is cleared to 0 ? when a match occurs between tm50 and cr50 (ii) tm60 ? after reset ? when the tce60 flag is cleared to 0 ? when a match occurs between tm60 and cr60 ? when a match occurs between tm60 and crh60
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 143 (d) pwm output mode (i) tm50 ? after reset ? when the tce50 flag is cleared to 0 ? when a match occurs between tm50 and cr50 ? when the tm50 count value overflows (ii) tm60 ? reset ? when the tce60 flag is cleared to 0 ? when a match occurs between tm60 and crh60 ? when the tm60 count value overflows
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 144 7.3 registers controlling 8-bit timers 50, 60 8-bit timers 50 and 60 are controlled by the following five registers. ? 8-bit timer mode control register 50 (tmc50) ? 8-bit timer mode control register 60 (tmc60) ? carrier generator output c ontrol register 60 (tca60) ? port mode register 3 (pm3) ? port 3 (p3) (1) 8-bit timer mode control register 50 (tmc50) 8-bit timer mode control register 50 (tmc50) is us ed to control the timer 50 count clock setting and the operation mode setting. tmc50 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc50 to 00h.
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 145 figure 7-4. format of 8-bit timer mode control register 50 symbol <7> <6> 5 4 3 2 1 <0> address after reset r/w tmc50 tce50 teg50 tcl502 tcl501 tcl500 tmd501 tmd500 toe50 ff4dh 00h r/w tce50 control of tm50 count operation note 1 0 clears tm50 count value and stops operation 1 starts count operation teg50 valid edge selection for tm50 count clock 0 counts at the rising edge of the count clock 1 counts at both edges of the count clock note 2 tcl502 tcl501 tcl500 selection of timer 50 count clock 0 0 0 f x (5.0 mhz) 0 0 1 f x /2 3 (625 khz) 0 1 0 f x /2 7 (39.1 khz) 0 1 1 f xt (32.768 khz) 1 0 0 timer 60 match signal 1 0 1 carrier clock (in carrier generator mode) or timer 60 output signal (in a mode other than carrier generator mode) other than above setting prohibited tmd501 tmd500 tmd601 tmd600 selection of operation mode for timer 50 and timer 60 note 3 0 0 0 0 discrete mode (8-bit timer counter mode) 0 1 0 1 cascade connection mode (16-bit timer counter mode) 0 0 1 1 carrier generator mode 0 0 1 0 timer 50: discrete mode (8-bit counter mode) timer 60: pwm pulse generator mode 1 0 1 0 timer 50: pwm free-running mode timer 60: pwm pulse generator mode 1 0 0 0 timer 50: pwm free-running mode timer 60: discrete mode (8-bit counter mode) other than above setting prohibited toe50 control of timer output 0 output disabled 1 output enabled
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 146 notes 1. since the count operation is cont rolled by tce60 (bit 7 of tmc 60) in cascade connection mode, any setting for tce50 is ignored. 2. the selection of both edges is va lid only in the pwm output mode. in 8-bit counter mode or cascade connection mode, counting is done using the ri sing edge even if teg50 is set to ?1?. 3. the operation mode selection is set to bot h the tmc50 register and tmc60 register. cautions 1. in cascade connection mode, the output si gnal of timer 60 is forcibly selected as the count clock. 2. when operating tmc50, be sure to perform settings in the following order. <1> stop tm50 count operation. <2> set the operation m ode and the count clock. <3> start count operation. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation) (2) 8-bit timer mode control register 60 (tmc60) 8-bit timer mode control register 60 (tmc60) is us ed to control the timer 60 count clock setting and the operation mode setting. tmc60 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc60 to 00h.
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 147 figure 7-5. format of 8-bit timer mode control register 60 symbol <7> <6> 5 4 3 2 1 <0> address after reset r/w tmc60 tce60 toe61 tcl602 tcl601 tcl600 tmd601 tmd600 toe60 ff4eh 00h r/w tce60 control of tm60 count operation note 1 0 clears tm60 count value and stops operation (the count value is also cleared for tm50 in cascade connection mode) 1 starts count operation (the c ount operation is also started fo r tm50 in cascade connection mode) tcl602 tcl601 tcl600 selection of timer 60 count clock 0 0 0 f x (5.0 mhz) 0 0 1 f x /2 2 (1.25 mhz) 0 1 0 f tmi (external input clock) 0 1 1 f tmi /2 (external input clock) 1 0 0 f tmi /2 2 (external input clock) 1 0 1 f tmi /2 3 (external input clock) other than above setting prohibited tmd501 tmd500 tmd601 tmd600 selection of operation mode for timer 50 and timer 60 note 2 0 0 0 0 discrete mode (8-bit timer counter mode) 0 1 0 1 cascade connection mode (16-bit timer counter mode) 0 0 1 1 carrier generator mode 0 0 1 0 timer 50: discrete mode (8-bit counter mode) timer 60: pwm pulse generator mode 1 0 1 0 timer 50: pwm free-running mode timer 60: pwm pulse generator mode 1 0 0 0 timer 50: pwm free-running mode timer 60: discrete mode (8-bit counter mode) other than above setting prohibited toe61 toe60 control of timer output 0 0 output disabled 0 1 output enabled only for to60 1 0 output enabled only for to61 1 1 setting prohibited notes 1. since the count operation is cont rolled by tce60 (bit 7 of tmc 60) in cascade connection mode, any setting for tce50 is ignored. 2. the operation mode selection is set to bot h the tmc50 register and tmc60 register.
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 148 caution when operating the tmc60, be sure to perform settings in the following order. <1> stop the tm60 count operation. <2> set the operation mode and the count clock. <3> start count operation. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. (3) carrier generator output control register 60 (tca60) this register is used to set the time r output data in carrier generator mode. tca60 is set with an 8-bit memo ry manipulation instruction. reset input sets tca60 to 00h. figure 7-6. format of carrier gene rator output control register 60 symbol 7 6 5 4 3 <2> <1> <0> address after reset r/w tca60 0 0 0 0 0 rmc60 nrzb60 nrz60 ff4fh 00h w rmc60 control of remote control output 0 when nrzb60 = 1, a carrier pulse is output. when nrzb60 = 0, a low level is output. 1 when nrzb60 = 1, high-level signal is output. when nrzb60 = 0, a low level is output. nrzb60 this is the bit that stores the next data to be output to nrz60. when a match signal occurs (for a match with timer 50), the data is output to nrz60. input the required value to nrz60 by program beforehand. nrz60 no return zero data 0 outputs low-level signal (carrier clock is stopped) 1 outputs carrier pulse
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 149 cautions 1. bits 3 to 7 must be set to 0. 2. tca60 cannot be set with a 1-bit memory mani pulation instruction. be sure to use an 8- bit memory manipulation in struction to set tca60. 3. the nrz60 flag can be written only when carrier generator output is stopped (toe60 = 0). the data cannot be o verwritten when toe60 = 1. 4. when the carrier generator is stopped once and then started again, nrzb60 does not hold the previous data. re-set data to nrzb60. at this time, a 1-bit memory manipulation instruction must not be used . be sure to use an 8-bit memory manipulation instruction. 5. while inttm50 (interrupt generated by the match signal of timer 50) is being output, accessing tca60 is prohibited. 6. accessing tca60 is prohibited while 8- bit timer counter 50 (tm50) is 00h. to access tca60 while tm50 = 00h, wait for mo re than half a period of the tm50 count clock and then rewrite tca60. 7. to enable operation in the carrier generator mode, set a val ue to the compare registers (cr50, cr60, and crh60), and input th e necessary value to the nrzb60 and nrz60 flags in advance. otherwise, the signal of the timer matc h circuit will become unstable and the nrz60 flag will be undefined. (4) port mode register 3 (pm3) this register is used to set the i/o mode of port 3 in 1-bit units. when using the p31/to50/intp1/tmi60 pin as a time r output, set pm31 and the p31 output latch to 0. when using the p31/to50/intp1/tmi60 pi n as a timer input, set pm31 to 1. when using the p32/to60/intp2 pin as a timer output, set the pm32 and p32 output latch to 0. when using the p33/to61/intp3 pin as a timer output, set the pm33 and p33 output latch to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 7-7. format of port mode register 3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pm3 1 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w pm3n i/o mode of p3n pin (n = 0 to 3) 0 output mode (output buffer is on) 1 input mode (output buffer is off)
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 150 7.4 8-bit timers 50, 60 operation 7.4.1 operation as 8-bit timer counter timer 50 and timer 60 can be independently used as 8-bit timer counters. the following modes can be used for the 8-bit timer counter. ? interval timer with 8-bit resolution ? external event counter with 8- bit resolution (timer 60 only) ? square wave output with 8-bit resolution (1) operation as interval timer with 8-bit resolution the interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register n0 (crn0). to operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter n0 (tmn0) (tcen0 = 0). <2> disable timer output of ton0 (toen0 = 0). <3> set a count value in crn0. <4> set the operation mode of timer n0 to 8-bit timer counter mode (see figures 7-4 and 7-5 ). <5> set the count clock for timer n0 (see tables 7-3 and 7-4 ). <6> enable the operation of tmn0 (tcen0 = 1). when the count value of 8-bit timer counter n0 (tmn0) matches the val ue set in crn0, tmn0 is cleared to 00h and continues counting. at the same time, an interrupt request signal (inttmn0) is generated. tables 7-3 to 7-6 show interval time, and figures 7-8 to 7-13 show the timing of t he interval timer operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data. remark n = 5, 6
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 151 table 7-3. interval time of timer 50 tcl502 tcl501 tcl500 minimum interval time maximum interval time resolution 0 0 0 1/f x (0.2 s) 2 8 /f x (51.2 s) 1/f x (0.2 s) 0 0 1 2 3 /f x (1.6 s) 2 11 /f x (409.6 s) 2 3 /f x (1.6 s) 0 1 0 2 7 /f x (25.6 s) 2 15 /f x (6.55 ms) 2 7 /f x (25.6 s) 0 1 1 1/f xt (30.5 s) 2 8 /f xt (7.81 ms) 1/f xt (30.5 s) 1 0 0 input cycle of timer 60 match signal input cycle of timer 60 match signal 2 8 input cycle of timer 60 match signal 1 0 1 input cycle of timer 60 output input cycle of timer 60 output 2 8 input cycle of timer 60 remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency table 7-4. interval time of timer 60 tcl602 tcl601 tcl600 minimum interval time maximum interval time resolution 0 0 0 1/f x (0.2 s) 2 8 /f x (51.2 s) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 10 /f x (2.04 ms) 2 2 /f x (0.8 s) 0 1 0 f tmi input cycle f tmi input cycle 2 8 f tmi input cycle 0 1 1 f tmi /2 input cycle f tmi /2 input cycle 2 8 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 8 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 8 f tmi /2 3 input cycle remark f x : main system clock oscillation frequency
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 152 figure 7-8. timing of interval timer oper ation with 8-bit resolution (basic operation) count stop count clock crn0 tcen0 inttmn0 tonm n t tmn0 n 00h 01h n 00h 01h n 00h 00h 01h 00h 01h clear clear clear count start interrupt acknowledgement interrupt acknowledgement interrupt acknowledgement interval time interval time interval time remarks 1. interval time = (n + 1) t: n = 00h to ffh 2. n = 5, 6 nm = 50, 60, 61 figure 7-9. timing of interval timer operati on with 8-bit resolution (when crn0 is set to 00h) count clock crn0 tcen0 inttmn0 tonm 00h tmn0 00h count start remark n = 5, 6 nm = 50, 60, 61
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 153 figure 7-10. timing of interval timer operati on with 8-bit resolution (when crn0 is set to ffh) count clock crn0 tcen0 inttmn0 tonm ffh tmn0 ffh 00h 01h 00h 01h 00h ffh 00h 01h ffh ffh 00h clear clear clear count start remark n = 5, 6 nm = 50, 60, 61 figure 7-11. timing of interval ti mer operation with 8-bit resolution (when crn0 changes from n to m (n < m)) count clock crn0 tcen0 inttmn0 tonm tmn0 n 00h 00h n 00h 01h 00h 01h m nm n m clear clear clear count start interrupt acknowledgement interrupt acknowledgement crn0 overwritten remark n = 5, 6 nm = 50, 60, 61
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 154 figure 7-12. timing of interval ti mer operation with 8-bit resolution (when crn0 changes from n to m (n > m)) count clock crn0 tcen0 inttmn0 tonm tmn0 00h 00h 00h n ? 1 n mn m n m 00h ffh m h clear clear clear tmn0 overflows because m < n crn0 overwritten remark n = 5, 6 nm = 50, 60, 61 figure 7-13. timing of interval ti mer operation with 8-bit resolution (when timer 60 match signal is sel ected for timer 50 count clock) timer 60 count clock cr60 tce60 inttm60 to60 tm60 n 00h m 00h 00h 01h m n m 00h m 00h 00h 01h y ? 1 y 00h y 00h y input clock to timer 50 (timer 60 match signal) to50 inttm50 tce50 cr50 tm50 clear clear clear clear count start count start
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 155 (2) operation as external event counter with 8-bit resolution (timer 60 only) the external event counter counts t he number of external clock pulses input to the tmi60/p31/intp1/to50 pin by using 8-bit timer counter 60 (tm60). to operate timer 60 as an external event counter , settings must be made in the following sequence. <1> disable operation of 8-bit time r counter 60 (tm60) (tce60 = 0). <2> disable timer output of to60 (toe60 = 0). <3> set p31 to input mode (pm31 = 1). <4> select the external input clock for timer 60 (see table 7-5). <5> set the operation mode of timer 60 to 8-bi t timer counter mode (see figures 7-4 and 7-5). <6> set a count value in cr60. <7> enable the operati on of tm60 (tce60 = 1). each time the valid edge is input, the value of tm60 is incremented. when the count value of tm60 matc hes the value set in cr60, tm60 is cleared to 00h and continues counting. at the same time, an interr upt request signal (inttm60) is generated. figure 7-14 shows the timing of the external event counter operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data. figure 7-14. timing of operation of exte rnal event counter with 8-bit resolution tmi60 pin input tm60 count value cr60 tce60 inttm60 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n remark n = 00h to ffh
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 156 (3) operation as square-wave output with 8-bit resolution square waves of any frequency can be output at an interval specified by t he value preset in 8-bit compare register n0 (crn0). to operate timer n0 for square-wave output, se ttings must be made in the following sequence. <1> when using timer 50, set p31 to output mode (pm31 = 0). when using timer 60, set p32 to output mode (pm32 = 0) or set p33 to output mode (pm33 = 0) (when to61 is selected as timer output). <2> set the output latches of p31, p32, and p33 to 0. <3> disable operation of timer c ounter n0 (tmn0) (tcen0 = 0). <4> set a count clock for timer n0 and enable output of ton0 (toen0 = 1) note . <5> set a count value in crn0. <6> enable the operation of tmn0 (tcen0 = 1). when the count value of tmn0 matches the value set in crn0, the ton0 pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match occurs, tmn0 is cleared to 00h and continues counting. at the same time, an in terrupt request signal (inttmn0) is generated. the square-wave output is cleared to 0 by setting tcen0 to 0. tables 7-5 and 7-6 show the squar e-wave output range, and figure 7-15 shows the timing of square-wave output. note in the case of timer 60, either to60 or to61 can be selected as the time r output pin. if to61 is selected, set toe61 = 1. caution be sure to stop the timer operation before overwriting the count cl ock with different data. remark n = 5, 6 table 7-5. square-wave output range of timer 50 (during f x = 5.0 mhz operation) tcl502 tcl501 tcl500 minimum pulse width maximum pulse width resolution 0 0 0 1/f x (0.2 s) 2 8 /f x (51.2 s) 1/f x (0.2 s) 0 0 1 2 3 /f x (1.6 s) 2 11 /f x (409.6 s) 2 3 /f x (1.6 s) 0 1 0 2 7 /f x (25.6 s) 2 15 /f x (6.55 ms) 2 7 /f x (25.6 s) 0 1 1 1/f xt (30.5 s) 2 8 /f xt (7.81 ms) 1/f xt (30.5 s) 1 0 0 input cycle of timer 60 match signal input cycle of timer 60 match signal 2 8 input cycle of timer 60 match signal 1 0 1 input cycle of timer 60 output input cycle of timer 60 output 2 8 input cycle of timer 60 remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 157 table 7-6. square-wave output range of timer 60 (during f x = 5.0 mhz operation) tcl6 02 tcl601 tcl600 minimum pulse width maximum pulse width resolution 0 0 0 1/f x (0.2 s) 2 8 /f x (51.2 s) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 10 /f x (2.04 ms) 2 2 /f x (0.8 s) 0 1 0 f tmi input cycle f tmi input cycle 2 8 f tmi input cycle 0 1 1 f tmi /2 input cycle f tmi /2 input cycle 2 8 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 8 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 8 f tmi /2 3 input cycle remark f x : main system clock oscillation frequency figure 7-15. timing of square-wave output with 8-bit resolution count clock crn0 tcen0 inttmn0 tonm note n tmn0 n 00h 01h n 00h 01h n 00h 01h 00h 01h clear clear clear count start interrupt acknowledgement interrupt acknowledgement interrupt acknowledgement note the initial value of tonm is low level when output is enabled (toenm = 1). remark n = 5, 6 nm = 50, 60, 61
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 158 7.4.2 operation as 16-bit timer counter timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. in this case, 8-bit timer counter 50 (tm50) is the higher 8 bits and 8-bit timer counter 60 (tm60) is the lower 8 bits. 8-bit timer 60 controls reset and clear. the following modes can be used for the 16-bit timer counter. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square-wave output with 16-bit resolution (1) operation as interval timer with 16-bit resolution the interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register 50 (cr50) and 8-bit compare register 60 (cr60). to operate as an interval timer with 16-bit resoluti on, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter 50 (tm 50) and 8-bit timer counter 60 (tm60) (tce50 = 0, tce60 = 0). <2> disable timer output of to60 (toe60 = 0). <3> set the count clock for timer 60 (see table 7-7 ). <4> set the operation mode of timer 50 and ti mer 60 to 16-bit timer counter mode (see figures 7-4 and 7- 5 ). <5> set a count value in cr50 and cr60. <6> enable the operation of tm50 and tm60 (tce60 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce60 (the value of tce50 is invalid). when the count values of tm50 and tm60 match the values set in cr50 and cr60 respectively, both tm50 and tm60 are simultaneously cleared to 00h and counting continues. at the same time, an interrupt request signal (inttm60) is generated (i nttm50 is not generated). table 7-7 shows interval time, and figure 7-16 show s the timing of the interval timer operation. cautions 1. be sure to stop the timer operation before overwriting th e count clock with different data. 2. in the 16-bit timer counter mode, to50 cannot be used. be sure to set toe50 = 0 to disable to50 output.
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 159 table 7-7. interval time with 16-bit resolution (during f x = 5.0 mhz operation) tcl602 tcl601 tcl600 minimum interval time maximum interval time resolution 0 0 0 1/f x (0.2 s) 2 16 /f x (13.1 ms) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 18 /f x (52.4 ms) 2 2 /f x (0.8 s) 0 1 0 f tmi input cycle f tmi input cycle 2 16 f tmi input cycle 0 1 1 f tmi /2 input cycle f tmi /2 input cycle 2 16 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 16 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 16 f tmi /2 3 input cycle remark f x : main system clock oscillation frequency
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 160 interval time count clock tm60 count value cr60 tce60 inttm60 to60 or to61 ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x x ? 1 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h t not cleared because tm50 does not match cleared because tm50 and tm60 match simultaneously count start interrupt not generated because tm50 does not match interrupt acknowledgement interrupt acknowledgement remark interval time = (256x + n + 1) t: x = 00h to ffh, n = 00h to ffh figure 7-16. timing of interval ti mer operation with 16-bit resolution
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 161 (2) operation as external event counter with 16-bit resolution the external event counter counts t he number of external clock pulses input to the tmi60/p31/intp1/to50 pin by tm50 and tm60. to operate as an external event c ounter with 16-bit resolution, setti ngs must be made in the following sequence. <1> disable operation of tm50 and tm60 (tce50 = 0, tce60 = 0). <2> disable timer output of to60 (toe60 = 0). <3> set p31 to input mode (pm31 = 1). <4> select the external input clock for timer 60 (see tables 7-5 and 7-6 ). <5> set the operation mode of timer 50 and ti mer 60 to 16-bit timer counter mode (see figures 7-4 and 7- 5 ). <6> set a count value in cr50 and cr60. <7> enable the operation of tm50 and tm60 (tce60 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce60 (the value of tce50 is invalid). each time the valid edge is input, the values of tm50 and tm60 are incremented. when the count values of tm50 and tm60 simult aneously match the values set in cr50 and cr60 respectively, both tm50 and tm60 are cleared to 00h and c ounting continues. at the same time, an interrupt request signal (inttm60) is generat ed (inttm50 is not generated). figure 7-17 shows the timing of the external event counter operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data.
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 162 tmi60 pin input tm60 count value cr60 tce60 inttm60 ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h x ? 1 not cleared because tm50 does not match cleared because tm50 and tm60 match simultaneously count start interrupt not generated because tm50 does not match interrupt acknowledgement interrupt acknowledgement remark x = 00h to ffh, n = 00h to ffh figure 7-17. timing of external event counter operation with 16-bit resolution
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 163 (3) operation as square-wave output with 16-bit resolution square waves of any frequency can be out put at an interval specified by the count value preset in cr50 and cr60. to operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1> disable operation of tm50 and tm60 (tce50 = 0, tce60 = 0). <2> disable output of to50, to60, and to 61 (toe50 = 0, toe60 = 0, toe61 = 0). <3> set the count clock for timer 60 (see table 7-7 ). <4> select either to60 or to 61 as the timer output pin. if to60 is selected: set p32 to the output mode (pm32 = 0), set the p32 output latch to 0, and set to60 to output enable (toe60 = 1). (use of to50 is prohibited.) if to61 is selected: set p33 to the output mode (pm33 = 0), set the p33 output latch to 0, and set to61 to output enable (toe61 = 1). (use of to50 is prohibited.) <5> set the operation mode of timer 50 and ti mer 60 to 16-bit timer counter mode (see figures 7-4 and 7- 5 ). <6> set count values in cr50 and cr60. <7> enable the operati on of tm60 (tce60 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce60 (the value of tce50 is invalid). when the count values of tm50 and tm60 simult aneously match the values set in cr50 and cr60 respectively, the to60 pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match o ccurs, tm50 and tm60 are cleared to 00h and counting continues. at the same time, an interrupt request si gnal (inttm60) is generated (inttm50 is not generated). the square-wave output is cleared to 0 by setting tce60 to 0. table 7-8 shows the square wave output range, and figure 7-18 show s timing of square wave output. cautions 1. be sure to stop the timer operation before overwriting the count clock with different data. 2. in the 16-bit timer counter mode, to50 ca nnot be used. be sure to set toe50 = 0 to disable to50 output. remark items in parentheses are for when the to61 pin is selected for timer output. table 7-8. square-wave output ra nge with 16-bit resolution (during f x = 5.0 mhz operation) tcl602 tcl601 tcl600 minimum pulse width maximum pulse width resolution 0 0 0 1/f x (0.2 s) 2 16 /f x (13.1 ms) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 18 /f x (52.4 ms) 2 2 /f x (0.8 s) 0 1 0 f tmi input cycle f tmi input cycle 2 16 f tmi input cycle 0 1 1 f tmi /2 input cycle f tmi /2 input cycle 2 16 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 16 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 16 f tmi /2 3 input cycle remark f x : main system clock oscillation frequency
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 164 count clock tm60 count value cr60 tce60 inttm60 to60 or to61 note ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm50 count pulse tm50 00h x x ? 1 01h cr50 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h not cleared because tm50 does not match cleared because tm50 and tm60 match simultaneously count start interrupt not generated because tm50 does not match interrupt acknowledgement interrupt acknowledgement figure 7-18. timing of square-wave output with 16-bit resolution note the initial value of to60 or to61 is low level when output is enabled. remark x = 00h to ffh, n = 00h to ffh
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 165 7.4.3 operation as carrier generator an arbitrary carrier clock generated by tm 60 can be output in the cycle set in tm50. to operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence. <1> disable operation of tm50 and tm60 (tce50 = 0, tce60 = 0). <2> disable timer output of to50 and to60 (toe50 = 0, toe60 = 0). <3> set count values in cr50, cr60, and crh60. <4> set the operation mode of timer 50 and timer 60 to carrier generator mode (see figures 7-4 and 7-5 ). <5> set the count clock for timer 50 and timer 60. <6> set remote control output to carrier pulse (rmc60 (bit 2 of carrier generator output control register 60 (tca60)) = 0). input the required value to nrzb 60 (bit 1 of tca60) by program. input a value to nrz60 (bit 0 of tca 60) before it is reloaded from nrzb60. <7> select either to60 or to 61 as the timer output pin. if to60 is selected: set p32 to the output mode (pm 32 = 0), set the p32 output latch to 0, and set toe60 to output enable (toe60 = 1). if to61 is selected: set p33 to the output mode (pm 33 = 0), set the p33 output latch to 0, and set toe61 to output enable (toe60 = 1). <8> enable the operation of tm50 and tm60 (tce50 = 1, tce60 = 1). the operation of the carrier generator is as follows. <1> when the count value of tm60 ma tches the value set in cr60, an in terrupt request signal (inttm60) is generated and output of timer 60 is in verted, which makes the compare register switch from cr60 to crh60. <2> after that, when the count value of tm60 matches the value set in crh60, an interrupt request signal (inttm60) is generated and output of ti mer 60 is inverted again, which make s the compare register switch from crh60 to cr60. <3> the carrier clock is generated by repeating <1> and <2> above. <4> when the count value of tm50 ma tches the value set in cr50, an in terrupt request signal (inttm50) is generated. the rising edge of inttm50 is the data reload signal of nrz b60 and is transferred to nrz60. <5> when nrz60 is 1, a carrier clock is out put from the to60 pin (or the to61 pin).
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 166 cautions 1. tca60 cannot be set with a 1-bit memory manipulation instruction. be sure to use an 8- bit memory manipulation instruction. 2. the nrz60 flag can be rewritten only wh en the carrier generator output is stopped (toe60 = 0). the data of the flag is not changed even if a write instruction is executed while toe60 = 1. 3. when the carrier generator is stopped once and then started again, nrzb60 does not hold the previous data. re-set data to nrzb60. at this time, a 1-bit memory manipulation instruction must not be used . be sure to use an 8-bit memory manipulation instruction. 4. while inttm50 (interrupt generated by the match signal of timer 50) is being output, accessing tca60 is prohibited. 5. accessing tca60 is prohibited while 8-bi t timer counter 50 (tm50) is 00h. to access tca60 while tm50 = 00h, wait for more than half a period of the tm50 count clock and then rewrite tca60. 6. to enable operation in the carrier generator mode, set a val ue to the compare registers (cr50, cr60, and crh60), and input th e necessary value to the nrzb60 and nrz60 flags in advance. otherwise, the signal of the timer matc h circuit will become unstable and the nrz60 flag will be undefined. figures 7-19 to 7-21 show the operat ion timing of the carrier generator.
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 167 figure 7-19. timing of carrier generato r operation (when cr60 = n, crh60 = m (m > n)) count clock tm60 count value cr60 tce60 inttm60 m 00h n 00h 01h n crh60 m n 00h carrier clock n 00h 00h n m 00h 01h l l 00h 01h l 00h 01h l 00h l 00h 01h tm50 cr50 tce50 inttm50 count pulse 0 1 0 10 0 1 01 0 nrzb60 nrz60 to60 or to61 carrier clock clear clear clear clear count start
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 168 figure 7-20. timing of carrier generato r operation (when cr60 = n, crh60 = m (m < n) count clock tm60 count value cr60 tce60 inttm60 n 00h n l crh60 m carrier clock n 00h 00h 01h l 00h 01h l 00h 01h l 00h l 00h 01h tm50 cr50 tce50 inttm50 count pulse 0 1 0 10 0 1 01 0 nrzb60 nrz60 to60 or to61 carrier clock m 00h m m 00h m 00h clear clear clear clear count start
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 169 figure 7-21. timing of carrier genera tor operation (when cr60 = crh60 = n) count clock tm60 count value cr60 tce60 inttm60 n 00h 00h 00h n crh60 n n carrier clock 00h 00h n n 00h 01h l 00h 01h l 00h 01h l 00h l 00h 01h tm50 cr50 tce50 inttm50 count pulse 0 1 0 10 0 1 01 0 nrzb60 nrz60 to60 or to61 carrier clock n n 00h clear clear clear clear clear count start
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 170 7.4.4 pwm free-running mode operation (timer 50) in the pwm free-running mode, to50 becomes high leve l when tm50 overflows, and to50 becomes low level when cr50 and tm50 match. it is thus possible to output a pulse with any duty ratio. to operate timer 50 in the pwm free-running mode, setting must be made in the following sequence. <1> disable operation of tm50 (tce50 = 0). <2> disable timer output of to50 (toe50 = 0). <3> set a count value to cr50. <4> set the operation mode of timer 50 to the pwm free-running mode (see figure 7-4 ). <5> set the count clock for timer 50. <6> set p31 to the output mode (p m31 = 0) and the p31 output latch to 0 and enable timer output of to50 (toe50 = 1). <7> enable the operation of tm50 (tce50 = 1). the operation in the pwm free-running mode is as follows. <1> when the count value of tm50 ma tches the value set in cr50, an in terrupt request signal (inttm50) is generated and a low level is output by the to50. the tm50 continues counting without being cleared. <2> to50 outputs a high level when the tm50 overflows. a pulse of any duty is output by r epeating the above procedure. figures 7-22 to 7-25 show the operation timing in the pwm free-running mode.
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 171 figure 7-22. operation timing in pwm free-r unning mode (when rising edge is selected) count clock cr50 tce50 inttm50 to50 n tm50 n 00h 00h 00h 01h ffh n ffh n overflow overflow count start caution when the rising edge is selected, do not set the cr50 to 00h. if the cr50 is set to 00h, pwm output may not be performed normally. figure 7-23. operation timing when overwriti ng cr50 (when rising edge is selected) (1/2) (1) when setting cr50 > tm50 after overflow count clock cr50 tce50 inttm50 to50 n tm50 n 00h 00h 00h 01h ffh m ffh 01h m overflow overflow overflow count start cr50 overwrite
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 172 figure 7-23. operation timing when overwriti ng cr50 (when rising edge is selected) (2/2) (2) when setting cr50 < tm50 after overflow count clock cr50 tce50 inttm50 to50 n tm50 n 00h 00h 00h 01h ffh ffh 01h 01h 02h 01h overflow overflow overflow count start cr50 overwrite overflow occurs but no change takes place because to50 is high level. figure 7-24. operation timing in pwm free-running mode (when both edges are selected) (1/2) (1) cr50 = even number count clock cr50 tce50 inttm50 to50 2n tm50 2n 00h 00h 01h ffh ffh 2n 02h feh 01h 02h feh overflow overflow overflow count start
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 173 figure 7-24. operation timing in pwm free-running mode (when both edges are selected) (2/2) (2) when cr50 = odd number count clock cr50 tce50 inttm50 to50 2n + 1 tm50 2n + 1 00h 00h 01h ffh ffh 2n + 1 01h 01h 00h overflow overflow overflow count start caution when both edges are selected, do not set cr50 to 00h, 01h, and ffh. if the cr50 is set to these values, pwm output may not be performed normally. figure 7-25. operation timing in pwm free-running mode (when both edges are selected) (when cr50 is overwritten) count clock cr50 tce50 inttm50 to50 2n + 1 tm50 2n 00h 00h 00h 01h ffh ffh 01h 2n + 1 01h 02h feh 2n overflow overflow overflow count start cr50 overwrite
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 174 7.4.5 operation as pwm output (timer 60) in the pwm pulse generator mode, a pul se of any duty ratio can be output by setting a low-level width using cr60 and a high-level width using crh60. to operate timer 60 in pwm output mode, setti ngs must be made in the following sequence. <1> disable operation of tm60 (tce60 = 0). <2> disable timer output of to60 (toe60 = 0). <3> set count values in cr60 and crh60. <4> set the operation mode of timer 60 to the pwm pulse generator mode (see figure 7-5 ). <5> set the count clock for timer 60. <6> set p32 to the output mode (p m32 = 0) and the p32 output latch to 0 and enable timer output of to60 (toe60 = 1). <7> enable the operation of tm60 (tce60 = 1). the operation in the pwm out put mode is as follows. <1> when the count value of tm60 ma tches the value set in cr60, an in terrupt request signal (inttm60) is generated and output of timer 60 is in verted, which makes the compare register switch from cr60 to crh60. <2> a match between tm60 and cr60 clears the tm60 value to 00h and then counting starts again. <3> after that, when the count value of tm60 matches the value set in crh60, an interrupt request signal (inttm60) is generated and output of ti mer 60 is inverted again, which make s the compare register switch from crh60 to cr60. <4> a match between tm60 and crh60 clears the tm60 va lue to 00h and then counting starts again. a pulse of any duty ratio is output by repeating <1> to <4> above. fi gures 7-26 and 7-27 s how the operation timing in the pwm output mode.
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 175 figure 7-26. pwm pulse generato r mode timing (basic operation) count clock tm60 count value cr60 tce60 inttm60 00h n 00h 01h n crh60 m n to60 or to61 note 00h 00h 01h m 01h 01h m 00h clear clear clear clear count start note the initial value of to60 is low level when output is enabled (toe60 = 1). figure 7-27. pwm output mode timing (when cr60 and crh60 are overwritten) count clock tm60 count value cr60 tce60 inttm60 00h n 00h 01h n crh60 m n to60 or to61 note m x y 00h 00h x 00h x ym clear clear clear clear count start note the initial value of to60 is low level when output is enabled (toe60 = 1).
chapter 7 8-bit timers 50, 60 user?s manual u15075ej2v1ud 176 7.5 notes on using 8-bit timers 50, 60 (1) error on starting timer an error of up to 1 clock is included in the time between the timer being started and a match signal being generated. this is because 8-bit timer counter n0 (tm n0) is started asynchronously to the count pulse. figure 7-28. start timing of 8-bit timer counter count pulse tmn0 count value 00h 01h 02h 03h 04h timer start remark n = 5, 6 (2) setting of 8-bit compare register n0 8-bit compare register n0 (crn0) can be set to 00h. therefore, one pulse can be c ounted when the 8-bit timer oper ates as an event counter. remark n = 5, 6 figure 7-29. timing of operation as exte rnal event counter (8-bit resolution) tmi60 input cr60 00h tm60 count value 00h 00h 00h 00h interrupt request flag
user?s manual u15075ej2v1ud 177 chapter 8 watch timer 8.1 watch timer functions the watch timer has the following functions. ? watch timer ? interval timer the watch and interval timers can be used at the same time. figure 8-1 is a block diagram of the watch timer. figure 8-1. block diagram of watch timer f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selector clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector
chapter 8 watch timer user?s manual u15075ej2v1ud 178 (1) watch timer the 4.19 mhz main system clock or 32.768 khz subsyst em clock is used to issue an interrupt request (intwt) at 0.5-second intervals. caution when the main system clo ck is operating at 5.0 mhz, it ca nnot be used to generate a 0.5- second interval. in this case, the subsystem clock, which operates at 32.768 khz, should be used instead. (2) interval timer the interval timer is used to generate an interr upt request (intwti) at specified intervals. table 8-1. interval genera ted using the interval timer interval at f x = 5.0 mhz at f x = 4.19 mhz at f xt = 32.768 khz 2 4 1/f w 409.6 s 489 s 488 s 2 5 1/f w 819.2 s 978 s 977 s 2 6 1/f w 1.64 ms 1.96 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.82 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 8.2 watch timer configuration the watch timer includes the following hardware. table 8-2. watch timer configuration item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm)
chapter 8 watch timer user?s manual u15075ej2v1ud 179 8.3 watch timer control register the watch timer is controlled by the wa tch timer mode control register (wtm). ? watch timer mode c ontrol register (wtm) wtm selects a count clock for the watch timer and specif ies whether to enable operation of the timer. it also specifies the prescaler interval and how the 5-bit counter is controlled. wtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wtm to 00h. figure 8-2. format of watch timer mode control register watch timer count clock selection wtm7 prescaler interval selection wtm6 0 0 0 0 1 1 2 4 /f w (488 s) 2 5 /f w (977 s) 2 6 /f w (1.95 ms) 2 7 /f w (3.91 ms) 2 8 /f w (7.81 ms) 2 9 /f w (15.6 ms) wtm5 0 0 1 1 0 0 wtm4 0 1 0 1 0 1 control of 5-bit counter operation wtm1 0 1 cleared after stop started watch timer operation wtm0 0 1 operation disabled (both prescaler and timer cleared) operation enabled other than above f x /2 7 f xt (39.1 khz) (32.768 khz) setting prohibited wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm 76 54 symbol address after reset r/w ff4ah 00h r/w 3210 0 1 remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. the parenthesized values apply to operation at f w = 32.768 khz.
chapter 8 watch timer user?s manual u15075ej2v1ud 180 8.4 watch timer operation 8.4.1 operation as watch timer the main system clock (4.19 mhz) or subsystem clock (32.768 khz) is used to enable the watch timer to operate at 0.5-second intervals. the watch timer is used to generate an inte rrupt request at specified intervals. by setting bits 0 and 1 (wtm0 and wtm1) of the watch time r mode control register (wtm) to 1, the watch timer starts counting. by setting them to 0, the 5-bit counter is cleared and the watc h timer stops counting. it is possible to start the watch timer only from zero se conds by clearing wtm1 to 0 when the interval timer and watch timer operate at the same time. in this case, however, an error of up to 2 9 1/f w seconds may occur in the overflow (intwt) after the zero-second start of the watc h timer because the 9-bit prescaler is not cleared to 0. 8.4.2 operation as interval timer the interval timer is used to repeatedly generate an interrupt request at the interval s pecified by a preset count value. the interval can be selected by bits 4 to 6 (wtm4 to wtm6) of the watch timer m ode control register (wtm). table 8-3. interval time of interval timer wtm6 wtm5 wtm4 interval at f x = 5.0 mhz at f x = 4.19 mhz at f xt = 32.768 khz 0 0 0 2 4 1/f w 409.6 s 489 s 488 s 0 0 1 2 5 1/f w 819.2 s 978 s 977 s 0 1 0 2 6 1/f w 1.64 ms 1.96 ms 1.95 ms 0 1 1 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 1 0 0 2 8 1/f w 6.55 ms 7.82 ms 7.81 ms 1 0 1 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f w : watch timer clock frequency
chapter 8 watch timer user?s manual u15075ej2v1ud 181 figure 8-3. watch timer/inte rval timer operation timing 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti watch timer interrupt time (0.5 s) watch timer interrupt time (0.5 s) interval timer (t) t caution when operation of the wa tch timer and 5-bit counter opera tion is enabled by setting bit 0 (wtm0) of the watch mode timer mode control register (wtm) to 1, the interval until the first interrupt request (intwt) is gene rated after the register is set does not exactly match the watch timer interrupt time (0.5 s). this is because th ere is a delay of one 9-bit prescaler output cycle until the 5-bit counter starts counting. sub sequently, however, the intw t signal is generated at the specified intervals. remarks 1. f w : watch timer clock frequency 2. the parenthesized values apply to operation at f w = 32.768 khz.
user?s manual u15075ej2v1ud 182 chapter 9 watchdog timer 9.1 watchdog timer functions the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect a program runaw ay. when a runaway is detected, a non-maskable interrupt or the reset signal can be generated. table 9-1. watchdog timer runaway detection time runaway detection time at f x = 5.0 mhz 2 11 1/f x 410 s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency (2) interval timer the interval timer generates an interrupt at an arbitrary preset interval. table 9-2. interval time interval at f x = 5.0 mhz 2 11 1/f x 410 s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency
chapter 9 watchdog timer user?s manual u15075ej2v1ud 183 9.2 watchdog timer configuration the watchdog timer includes the following hardware. table 9-3. configuration of watchdog timer item configuration control registers watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) figure 9-1. block diagram of watchdog timer internal bus internal bus prescaler selector controller f x 2 6 f x 2 8 f x 2 10 3 7-bit counter wdtif wdtmk tcl22 tcl21 tcl20 watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) clear wdtm4 run wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f x 2 4
chapter 9 watchdog timer user?s manual u15075ej2v1ud 184 9.3 watchdog timer control registers the watchdog timer is controlled by the following two registers. watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) (1) watchdog timer clock select register (wdcs) this register sets the watchdog timer count clock. wdcs is set with an 8-bit memo ry manipulation instruction. reset input sets wdcs to 00h. figure 9-2. format of watchdog timer clock select register wdcs2 0 0 1 1 wdcs1 0 1 0 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 (312.5 khz) (78.1 khz) (19.5 khz) (4.88 khz) wdcs0 0 0 0 0 setting prohibited other than above watchdog timer count clock selection 2 11 /f x 2 13 /f x 2 15 /f x 2 17 /f x (410 s) (1.64 ms) (6.55 ms) (26.2 ms) interval 0 0 0 0 0 wdcs2 wdcs1 wdcs0 wdcs 76 54 symbol address after reset r/w ff42h 00h r/w 3210 remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 9 watchdog timer user?s manual u15075ej2v1ud 185 (2) watchdog timer mode register (wdtm) this register sets the operation mode of the watchdog timer, and enables /disables counting of the watchdog timer. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 9-3. format of watc hdog timer mode register run 0 1 watchdog timer operation selection note 1 stops counting. clears counter and starts counting. wdtm4 watchdog timer operation mode selection note 2 wdtm3 0 1 1 0 1 1 operation stop interval timer mode (generates a maskable interrupt upon overflow occurrence.) note 3 watchdog timer mode 1 (generates a non-maskable interrupt upon overflow occurrence.) watchdog timer mode 2 (starts reset operation upon overflow occurrence.) 0 0 run 0 0 wdtm4 wdtm3 0 0 0 wdtm <7> 6 5 4 symbol address after reset r/w fff9h 00h r/w 3210 notes 1. once run has been set (1), it cannot be cleared (0 ) by software. theref ore, when counting is started, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set (1), they cannot be cleared (0) by software. 3. the watchdog timer starts operation as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by setting run to 1, the actual overflow time is up to 0.8% shorter than the time set by th e watchdog timer clock sel ect register (wdcs). 2. to set watchdog timer mode 1 or 2, set wdtm 4 to 1 after confirming tmif4 (bit 0 of the interrupt request flag register 0 (if0)) is set to 0. when watchdog timer mode 1 or 2 is selected with tmif4 set to 1, a non-m askable interrupt is generated upon the completion of rewriting wdtm4.
chapter 9 watchdog timer user?s manual u15075ej2v1ud 186 9.4 watchdog timer operation 9.4.1 operation as watchdog timer the watchdog timer detects a program runaway when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (wdcs0 to wdcs2) of watchdog timer clock select register (wdcs). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 within the se t runaway detection time interval after the watchdog timer has been started. by setting run to 1, the watchdog timer can be cleared and start counting. if run is not se t to 1, and the runaway detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the watchdog timer before exec uting the stop instruction. cautions 1. the actual runaway detection time may be up to 0. 8% shorter than the set time. 2. when the subsystem cl ock is selected as the cpu cl ock, the watchdog timer count operation is stopped. even when the main syst em clock continues o scillating in this case, watchdog timer count ope ration is stopped. table 9-4. watchdog timer runaway detection time wdcs2 wdcs1 wdcs0 runaway detection time at f x = 5.0 mhz 0 0 0 2 11 1/f x 410 s 0 1 0 2 13 1/f x 1.64 ms 1 0 0 2 15 1/f x 6.55 ms 1 1 0 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency
chapter 9 watchdog timer user?s manual u15075ej2v1ud 187 9.4.2 operation as interval timer when bits 4 and 3 (wdtm4, wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value. select a count clock (or interval) by setting bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). the watchdog timer star ts operation as an interval timer when the run bit (bit 7 of wdtm) is set to 1. in interval timer mode, the interrupt mask flag (wdt mk) is valid, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the interval timer before ex ecuting the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when watchdog timer mode is selected), interval timer mode is not set unless the reset signal is input. 2. the interval time may be up to 0.8% shorter than the set time when wdtm has just been set. table 9-5. interval time of interval timer wdcs2 wdcs1 wdcs0 interval at f x = 5.0 mhz 0 0 0 2 11 1/f x 410 s 0 1 0 2 13 1/f x 1.64 ms 1 0 0 2 15 1/f x 6.55 ms 1 1 0 2 17 1/f x 26.2 ms f x : main system clock oscillation frequency
user?s manual u15075ej2v1ud 188 chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) 10.1 8-bit a/d converter functions the 8-bit a/d converter is an 8-bit resolution converter used to convert analog inputs into digital signals. this converter can control six channels (ani0 to ani5) of analog inputs. a/d conversion can only be started by software. one of analog inputs ani0 to ani5 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued each time a/d conversion is complete. 10.2 8-bit a/d converter configuration the 8-bit a/d converter incl udes the following hardware. table 10-1. configuration of 8-bit a/d converter item configuration analog inputs 6 channels (ani0 to ani5) registers successive approx imation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) analog input channel specific ation register 0 (ads0)
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 189 figure 10-1. block diagra m of 8-bit a/d converter sample & hold circuit voltage comparator successive approximation register (sar) controller 3 a/d conversion result register 0 (adcr0) tap selector av ss intad0 a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) internal bus av ss p-ch av dd ani4/p64 ani5/p65 ani0/p60 ani1/p61 ani2/p62 ani3/p63 selector adcs0 fr02 fr01 fr00 ads02 ads01 ads00 (1) successive approximation register (sar) the sar receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least signifi cant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) adcr0 holds the result of a/d conv ersion. each time a/d conversion ends, the conversion result in the successive approximation register is loaded into adcr0, which is an 8-bit register. adcr0 can be read with an 8-bit memo ry manipulation instruction. reset input makes adcr0 undefined. (3) sample & hold circuit the sample & hold circuit samples consecutive analog inputs from the input ci rcuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion.
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 190 (4) voltage comparator the voltage comparator compares an analog input with the volt age output by the series resistor string. (5) series resistor string the series resistor stri ng is configured between av dd and av ss . it generates the reference voltages with which analog inputs are compared. (6) ani0 to ani5 pins ani0 to ani5 are the 6-channel analog input pins fo r the a/d converter. they are used to receive the analog signals for a/d conversion. caution do not supply pins ani0 to ani5 with voltages that fall outside the rated range. if a voltage greater than av dd or less than av ss (even if within the absolute maximum rating) is applied to any of these pins, the conversion value fo r the corresponding channe l will be undefined. furthermore, the conversion val ues for the other channels may also be affected. (7) av ss pin the av ss pin is a ground potential pin for t he a/d converter. this pin must be held at the same potential as the v ss pin, even while the a/d c onverter is not being used. (8) av dd pin the av dd pin is an analog power supply pin for the a/d conv erter. this pin must be held at the same potential as the v dd pin, even while the a/d c onverter is not being used.
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 191 10.3 8-bit a/d converter control registers the 8-bit a/d converter is controll ed by the following two registers. a/d converter mode register 0 (adm0) analog input channel specific ation register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adm0 to 00h. figure 10-2. format of a/d converter mode register 0 a/d conversion control adcs0 0 1 a/d conversion time selection note 1 fr02 0 0 0 1 1 1 144/f x 120/f x 96/f x 72/f x 60/f x 48/f x fr01 0 0 1 0 0 1 (28.8 s) (24 s) (19.2 s) (14.4 s) (setting prohibited note 2 ) (setting prohibited note 2 ) fr00 0 1 0 0 1 0 other than above conversion disabled conversion enabled setting prohibited adcs0 0 fr02 fr01 fr00 0 0 0 adm0 <7> 6 5 4 symbol address after reset r/w ff80h 00h r/w 3210 notes 1. the specifications of fr02, fr 01, and fr00 must be such that the a/d conversion time is at least 14 s. 2. these bit combinations must not be used, as the a/d conversion time will fall below 14 s. cautions 1. bits 0 to 2 and 6 must be set to 0. 2. the result of conversion performed immediately after setting adcs0 is undefined. 3. the conversion result may be undefined after clearing adcs0. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 192 (2) analog input channel specification register 0 (ads0) ads0 specifies the port used to input the analog voltage to be converted to a digital signal. ads0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets ads0 to 00h. figure 10-3. format of analog input channel specification register 0 0 0 0 0 0 ads02 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification other than above ads02 0 0 0 0 1 1 ani0 ani1 ani2 ani3 ani4 ani5 setting prohibited ads01 0 0 1 1 0 0 ads00 0 1 0 1 0 1 caution bits 3 to 7 must be set to 0.
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 193 10.4 8-bit a/d converter operation 10.4.1 basic operation of 8-bit a/d converter <1> select a channel for a/d conversion, using analog input channel specificati on register 0 (ads0). <2> the voltage supplied to the selected analog input c hannel is sampled using the sample & hold circuit. <3> after sampling continues for a certain period of time , the sample & hold circuit is put on hold to keep the input analog voltage until a/d c onversion is completed. <4> bit 7 of the successive approximation register (sar) is set. the series resistor string tap voltage at the tap selector is set to half of av dd . <5> the series resistor string tap voltage is co mpared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half of av dd , the msb of sar is left set. if it is lower than half of av dd , the msb is reset. <6> bit 6 of sar is set automatically, and comparison sh ifts to the next stage. the next tap voltage of the series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows: ? bit 7 = 1: three quarters of av dd ? bit 7 = 0: one quarter of av dd the tap voltage is compared with the analog input voltage. bit 6 is set or reset according to the result of comparison. ? analog input voltage tap voltage: bit 6 = 1 ? analog input voltage < tap voltage: bit 6 = 0 <7> comparison is repeated until bit 0 of sar is reached. <8> when comparison is completed for all of the 8 bits, a signi ficant digital result is left in sar. this value is sent to and latched in a/d conversion result register 0 (adcr0). at t he same time, it is possible to generate an a/d conversion end in terrupt request (intad0). cautions 1. the first a/d conver sion value immediately after a/d c onversion has been started may be undefined. 2. in standby mode, a/d c onverter operation is stopped.
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 194 figure 10-4. basic operati on of 8-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcr0 intad0 80h c0h or 40h a/d conversion continues until bit 7 (adcs 0) of a/d converter mode register 0 (adm0) is reset (0) by software. if an attempt is made to write to adm0 or analog input channel specification regi ster 0 (ads0) during a/d conversion, the ongoing a/d conver sion is canceled. in this case, a/d conv ersion is restarted fr om the beginning, if adcs0 is set (1). reset input makes a/d conversion re sult register 0 (adcr0) undefined. 10.4.2 input voltage and conversion result the relationships between the analog input voltage at the analog input pi ns (ani0 to ani5) and the a/d conversion result (a/d conversion result register 0 (adcr0)) are represented by: adcr0 = int ( 256 + 0.5) or (adcr0 ? 0.5) v in < (adcr0 + 0.5) int( ): function that returns t he integer part of a parenthesized value v in : analog input voltage av dd : supply voltage for the a/d converter adcr0: value in a/d conversion result register 0 (adcr0) figure 10-5 shows the relationship between the anal og input voltage and the a/d conversion result. v in av dd av dd 256 av dd 256
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 195 figure 10-5. relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr0) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av dd
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 196 10.4.3 operation mode of 8-bit a/d converter the a/d converter is initially in select mode. in this mode, analog input channel specification regi ster 0 (ads0) is used to select an analog input channel from ani0 to ani5 for a/d conversion. a/d conversion can be started only by software, that is, by setting a/d converter mode register 0 (adm0). the a/d conversion result is saved to a/d conversion result register 0 (adcr0 ). at the same time, an interrupt request signal (intad0) is generated. ? software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 1 triggers a/d conversion for a voltage applied to the analog input pin specified in analog input channel specification r egister 0 (ads0). upon completion of a/d conversion, the conv ersion result is saved to a/d conver sion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. once a/d conv ersion is activated, and completed, another session of a/d conversion is started. a/d conversion is repeated unt il new data is written to adm0. if data where adcs0 is 1 is written to adm0 again during a/d conversion, the ongoing session of a/d conversion is discontinued, and a new session of a/d conversion begins for the new data. if data where adcs0 is 0 is written to adm0 again during a/d conversion, a/d conversi on is stopped immediately. figure 10-6. software-started a/d conversion rewriting adm0 adcs0 = 1 rewriting adm0 adcs0 = 1 adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0 to 5 2. m = 0 to 5
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 197 10.5 cautions related to 8-bit a/d converter (1) current consumpti on in standby mode in standby mode, the a/d converter stops operation. stopping conversion (bit 7 (adcs0) of a/d converter mode register 0 (adm0) = 0) can reduce the current consumption. figure 10-7 shows how to reduce the cu rrent consumption in standby mode. figure 10-7. how to reduce current consumption in standby mode av dd av ss p-ch series resistor string adcs0 (2) input range for pins ani0 to ani5 be sure to keep the input voltage at ani0 to an i5 within the rating. if a voltage not lower than av dd or not higher than av ss (even within the absolute maximum rating) is input into a conversion channel, the conversion output of the c hannel becomes undefined, which may affect the conversion out put of the other channels. (3) conflict <1> conflict between writing to a/d conversion result register 0 (a dcr0) at the end of conversion and reading from adcr0 using instruction reading from adcr0 takes precedence. after reading, the new conversion result is written to adcr0. <2> conflict between writing to adcr0 at the end of conversion and writing to a/d conv erter mode register 0 (adm0) or analog input channel spec ification register 0 (ads0) writing to adm0 or ads0 takes precedence. adcr0 is not written to. no a/d conversion end interrupt request signal (intad0) is generated. (4) conversion result immediatel y after start of a/d conversion the first a/d conversion value immediately after a/d conversion has been started is undefined. poll the a/d conversion end interrupt request (intad0) and drop the first conversion result.
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 198 (5) timing of undefined a/d conversion result the a/d conversion value may become undefined if the timing of the comp letion of a/d conversion and that to stop the a/d conversion operation conflict. therefore, read the a/d conversion result while the a/d conversion operation is in progress. to read the a/d conversion result after the a/d conversion operation has been stopped, stop the a/d conversion operation before the next conversion operat ion is completed. figures 10-8 and 10-9 show the timing at wh ich the conversion result is read. figure 10-8. conversion result read timi ng (if conversion result is undefined) end of a/d conversion end of a/d conversion normal conversion result undefined value normal conversion result is read. a/d conversion stops. undefined value is read. adcr0 intad0 adcs0 figure 10-9. conversion result read ti ming (if conversion result is normal) normal conversion result end of a/d conversion normal conversion result is read. a/d conversion stops. adcr0 intad0 adcs0
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 199 (6) noise prevention to maintain a resolution of 8 bits, watch for noise to the av dd and ani0 to ani5 pins. the higher the output impedance of the analog input s ource, the larger the effect by noise. to reduce noise, attach an external capacitor to the relevant pi ns as shown in figure 10-10. figure 10-10. analog input pin treatment c = 100 to 1,000 pf if noise not lower than av dd or not higher than av ss is likely to come to the av dd pin, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). av ss v ss av dd v dd (7) ani0 to ani5 the analog input pins (ani0 to ani5) are alternate-function pins. they are also used as port pins (p60 to p65). if any of ani0 to ani5 has been selected for a/d conver sion, do not execute input in structions for the ports; otherwise the conversion re solution may be reduced. if a digital pulse is applied to a pin adjacent to the analog input pins during a/d conversion, coupling noise may occur that prevents an a/d conv ersion result from being obtained as expected. avoid applying a digital pulse to pins adjacent to the analog input pins during a/d conversion. (8) interrupt request flag (adif0) changing the contents of a/d converter mode register 0 (adm0) does not clear the interrupt request flag (adif0). if the analog input pins are changed dur ing a/d conversion, t herefore, the a/d conv ersion result and the conversion end interrupt request flag may reflect the pr evious analog input immedi ately before writing to adm0 occurs. in this case, adif0 may already be set if it is read-accessed immediately after adm0 is write- accessed, even when a/d conversion has not been completed for the new analog input. in addition, when a/d conversion is rest arted, adif0 must be cleared beforehand.
chapter 10 8-bit a/d converter ( pd789426 and 789446 subseries) user?s manual u15075ej2v1ud 200 figure 10-11. a/d conversion end in terrupt request generation timing rewriting to adm0 (to begin conversion for anin) rewriting to adm0 (to begin conversion for anim) a/d conversion anin anin anim anim adif0 has been set, but conversion for anim has not been completed. adcr0 anin anin anim anim intad0 remarks 1. n = 0 to 5 2. m = 0 to 5 (9) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani5 input circuit. if your application is designed to be changed to backup power, the av dd pin must be supplied with the same voltage level as the v dd pin, as shown in figure 10-12. figure 10-12. av dd pin handling main power source backup capacitor v dd av dd v ss av ss (10) av dd pin input impedance a series resistor string of several ten of k ? is connected between the av dd and av ss pins. consequently, if the output impedance of the reference voltage supply is high, the reference voltage supply will form a parallel connection with the series resistor string, cr eating a large referenc e voltage differential.
user?s manual u15075ej2v1ud 201 chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) 11.1 10-bit a/d converter functions the 10-bit a/d converter is a 10-bit resolution converter used to convert analog inputs into digital signals. this converter can control six channels (ani0 to ani5) of analog inputs. a/d conversion can only be started by software. one of analog inputs ani0 to ani5 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued each time a/d conversion is complete. 11.2 10-bit a/d converter configuration the 10-bit a/d converter incl udes the following hardware. table 11-1. configuration of 10-bit a/d converter item configuration analog inputs 6 channels (ani0 to ani5) registers successive approx imation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) analog input channel specific ation register 0 (ads0)
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 202 figure 11-1. block diagra m of 10-bit a/d converter sample & hold circuit voltage comparator successive approximation register (sar) controller 3 a/d conversion result register 0 (adcr0) tap selector av ss intad0 a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) internal bus av ss p-ch av dd ani4/p64 ani5/p65 ani0/p60 ani1/p61 ani2/p62 ani3/p63 selector adcs0 fr02 fr01 fr00 ads02 ads01 ads00 (1) successive approximation register (sar) the sar receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least signifi cant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) adcr0 is a 16-bit register that holds t he result of a/d conversion. the lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion re sult in the successive approximati on register is loaded into adcr0. the higher 8 bits of the conversion result are loaded into ff15h of adcr0 and the lower 2 bits into ff14h, with the bit 15 as the most significant bit (msb). adcr0 can be read with a 16-bit memo ry manipulation instruction. reset input sets adcr0 to 0000h. adcr0 symbol ff15h 0 0 0 0 0 0 ff14h ff14h, ff15h address after reset 0000h r/w r caution when the pd78f9436, a flash memo ry version of the pd789425 or pd789426, is used, this register can be accessed in 8-bit units. however, only an object file assembled with the pd789425 or pd789426 can be used. the sam e is also true for the pd78f9456, a flash memory version of the pd789445 or pd789446: this register can be accessed in 8- bit units, but only an object file assembled with the pd789445 or pd789446 can be used.
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 203 (3) sample & hold circuit the sample & hold circuit samples consecutive analog inputs from the input ci rcuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion. (4) voltage comparator the voltage comparator compares an analog input with the volt age output by the series resistor string. (5) series resistor string the series resistor stri ng is configured between av dd and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani5 pins ani0 to ani5 are the 6-channel analog input pins fo r the a/d converter. they are used to receive the analog signals for a/d conversion. caution do not supply pins ani0 to ani5 with voltages that fall outside the rated range. if a voltage greater than av dd or less than av ss (even if within the absolute maximum rating) is applied to any of these pins, the conversion value fo r the corresponding channe l will be undefined. furthermore, the conversion val ues for the other channels may also be affected. (7) av ss pin the av ss pin is a ground potential pin for t he a/d converter. this pin must be held at the same potential as the v ss pin, even while the a/d c onverter is not being used. (8) av dd pin the av dd pin is an analog power supply pin for the a/d conv erter. this pin must be held at the same potential as the v dd pin, even while the a/d c onverter is not being used.
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 204 11.3 10-bit a/d converter control registers the 10-bit a/d converter is controll ed by the following two registers. a/d converter mode register 0 (adm0) analog input channel specific ation register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adm0 to 00h. figure 11-2. format of a/d converter mode register 0 a/d conversion control adcs0 0 1 a/d conversion time selection note 1 fr02 0 0 0 1 1 1 144/f x 120/f x 96/f x 72/f x 60/f x 48/f x fr01 0 0 1 0 0 1 (28.8 s) (24 s) (19.2 s) (14.4 s) (setting prohibited note 2 ) (setting prohibited note 2 ) fr00 0 1 0 0 1 0 other than above conversion disabled conversion enabled setting prohibited adcs0 0 fr02 fr01 fr00 0 0 0 adm0 <7> 6 5 4 symbol address after reset r/w ff80h 00h r/w 3210 notes 1. the specifications of fr02, fr 01, and fr00 must be such that the a/d conversion time is at least 14 s. 2. these bit combinations must not be used, as the a/d conversion time will fall below 14 s. cautions 1. bits 0 to 2 and 6 must be set to 0. 2. the result of conversion performed immediately after setting adcs0 is undefined. 3. the conversion result may be undefined after clearing adcs0. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 205 (2) analog input channel specification register 0 (ads0) ads0 specifies the port used to input the analog voltage to be converted to a digital signal. ads0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears ads0 to 00h. figure 11-3. format of analog input channel specification register 0 0 0 0 0 0 ads02 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification other than above ads02 0 0 0 0 1 1 ani0 ani1 ani2 ani3 ani4 ani5 setting prohibited ads01 0 0 1 1 0 0 ads00 0 1 0 1 0 1 caution bits 3 to 7 must be set to 0.
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 206 11.4 10-bit a/d converter operation 11.4.1 basic operation of 10-bit a/d converter <1> select a channel for a/d conversion, using analog input channel specificati on register 0 (ads0). <2> the voltage supplied to the selected analog input c hannel is sampled using the sample & hold circuit. <3> after sampling continues for a certain period of time , the sample & hold circuit is put on hold to keep the input analog voltage until a/d c onversion is completed. <4> bit 9 of the successive approximation register (sar) is set. the series resistor string tap voltage at the tap selector is set to half of av dd . <5> the series resistor string tap voltage is co mpared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half of av dd , the msb of sar is left set. if it is lower than half of av dd , the msb is reset. <6> bit 8 of sar is set automatically, and comparison sh ifts to the next stage. the next tap voltage of the series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows: ? bit 9 = 1: three quarters of av dd ? bit 9 = 0: one quarter of av dd the tap voltage is compared with the analog input voltage. bit 8 is set or reset according to the result of comparison. ? analog input voltage tap voltage: bit 8 = 1 ? analog input voltage < tap voltage: bit 8 = 0 <7> comparison is repeated until bit 0 of sar is reached. <8> when comparison is completed for all of the 10 bits, a signi ficant digital result is le ft in sar. this value is sent to and latched in a/d conversion result register 0 (adcr0). at t he same time, it is possible to generate an a/d conversion end in terrupt request (intad0). cautions 1. the first a/d conver sion value immediately after a/d c onversion has been started may be undefined. 2. in standby mode, a/d c onverter operation is stopped.
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 207 figure 11-4. basic operati on of 10-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcr0 intad0 a/d conversion continues until bit 7 (adcs 0) of a/d converter mode register 0 (adm0) is reset (0) by software. if an attempt is made to write to adm0 or analog input channel specification regi ster 0 (ads0) during a/d conversion, the ongoing a/d conver sion is canceled. in this case, a/d conv ersion is restarted fr om the beginning, if adcs0 is set (1). reset input makes a/d conversion re sult register 0 (adcr0) undefined. 11.4.2 input voltage and conversion result the relationships between the analog input voltage at the analog input pi ns (ani0 to ani5) and the a/d conversion result (a/d conversion result register 0 (adcr0)) are represented by: adcr0 = int ( 1,024 + 0.5) or (adcr0 ? 0.5) v in < (adcr0 + 0.5) int( ): function that returns t he integer part of a parenthesized value v in : analog input voltage av dd : supply voltage for the a/d converter adcr0: value in a/d conversion result register 0 (adcr0) figure 11-5 shows the relationship between the anal og input voltage and the a/d conversion result. v in av dd av dd 1,024 av dd 1,024
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 208 figure 11-5. relationship between analog input voltage and a/d conversion result 1023 1022 1021 3 2 1 0 a/d conversion result (adcr0) 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 input voltage/av dd
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 209 11.4.3 operation mode of 10-bit a/d converter the a/d converter is initially in select mode. in this mode, analog input channel specification regi ster 0 (ads0) is used to select an analog input channel from ani0 to ani5 for a/d conversion. a/d conversion can be started only by software, that is, by setting a/d converter mode register 0 (adm0). the a/d conversion result is saved to a/d conversion result register 0 (adcr0 ). at the same time, an interrupt request signal (intad0) is generated. ? software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 1 triggers a/d conversion for a voltage applied to the analog input pin specified in a/d input selection register 0 (ads0). upon completion of a/d conversion, the conversion result is saved to a/d c onversion result register 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. once a/d c onversion is activated, and completed, another session of a/d conversion is started. a/d conversion is repeated unt il new data is written to adm0. if data where adcs0 is 1 is written to adm0 agai n during a/d conversion, the ongoing session of a/d conversion is discontinued, and a new session of a/d conversion begins for the new data. if data where adcs0 is 0 is written to adm0 agai n during a/d conversion, a/d conversion is stopped immediately. figure 11-6. software-started a/d conversion rewriting adm0 adcs0 = 1 overwriting adm0 adcs0 = 1 adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0 to 5 2. m = 0 to 5
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 210 11.5 cautions related to 10-bit a/d converter (1) current consumpti on in standby mode in standby mode, the a/d converter stops operation. stopping conversion (bit 7 (adcs0) of a/d converter mode register 0 (adm0) = 0) can reduce the current consumption. figure 11-7 shows how to reduce the cu rrent consumption in standby mode. figure 11-7. how to reduce current consumption in standby mode av dd av ss p-ch series resistor string adcs0 (2) input range for pins ani0 to ani5 be sure to keep the input voltage at ani0 to an i5 within the rating. if a voltage not lower than av dd or not higher than av ss (even within the absolute maximum rating) is input into a conversion channel, the conversion output of the c hannel becomes undefined, which may affect the conversion out put of the other channels. (3) conflict <1> conflict between writing to a/d conversion result register 0 (a dcr0) at the end of conversion and reading from adcr0 using instruction reading from adcr0 takes precedence. after reading, the new conversion result is written to adcr0. <2> conflict between writing to adcr0 at the end of conversion and writing to a/d conv erter mode register 0 (adm0) or analog input channel spec ification register 0 (ads0) writing to adm0 or ads0 takes precedence. adcr0 is not written to. no a/d conversion end interrupt request signal (intad0) is generated. (4) conversion result immediatel y after start of a/d conversion the first a/d conversion value immediately after a/d conversion has been started is undefined. poll the a/d conversion end interrupt request (intad0) and drop the first conversion result.
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 211 (5) timing of undefined a/d conversion result the a/d conversion value may become undefined if the timing of the comp letion of a/d conversion and that to stop the a/d conversion operation conflict. therefore, read the a/d conversion result while the a/d conversion operation is in progress. to read the a/d conversion result after the a/d conversion operation has been stopped, stop the a/d conversion operation before the next conversion operat ion is completed. figures 11-8 and 11-9 show the timing at wh ich the conversion result is read. figure 11-8. conversion result read timi ng (if conversion result is undefined) end of a/d conversion end of a/d conversion normal conversion result undefined value normal conversion result is read. a/d conversion stops. undefined value is read. adcr0 intad0 adcs0 figure 11-9. conversion result read ti ming (if conversion result is normal) normal conversion result end of a/d conversion normal conversion result is read. a/d conversion stops. adcr0 intad0 adcs0
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 212 (6) noise prevention to maintain a resolution of 10 bits, watch for noise to the av dd and ani0 to ani5 pins. the higher the output impedance of the analog i nput source, the larger the effect by noise. to reduce noise, attach an external capacitor to the relevant pins as shown in figure 11-10. figure 11-10. analog input pin treatment c = 100 to 1,000 pf if noise not lower than av dd or not higher than av ss is likely to come to the av dd pin, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). av ss v ss av dd v dd (7) ani0 to ani5 the analog input pins (ani0 to ani5) are alternate-function pins. they are also used as port pins (p60 to p65). if any of ani0 to ani5 has been selected for a/d conver sion, do not execute input in structions for the ports; otherwise the conversion re solution may be reduced. if a digital pulse is applied to a pin adjacent to the analog input pins during a/d conversion, coupling noise may occur that prevents an a/d conv ersion result from being obtained as expected. avoid applying a digital pulse to pins adjacent to the analog input pins during a/d conversion. (8) interrupt request flag (adif0) changing the contents of a/d converter mode register 0 (adm0) does not clear the interrupt request flag (adif0). if the analog input pins are changed dur ing a/d conversion, t herefore, the a/d conv ersion result and the conversion end interrupt request flag may reflect the pr evious analog input immedi ately before writing to adm0 occurs. in this case, adif0 may already be set if it is read-accessed immediately after adm0 is write- accessed, even when a/d conversion has not been completed for the new analog input. in addition, when a/d conversion is rest arted, adif0 must be cleared beforehand.
chapter 11 10-bit a/d converter ( pd789436 and 789456 subseries) user?s manual u15075ej2v1ud 213 figure 11-11. a/d conversion end in terrupt request generation timing a/d conversion adcr0 intad0 rewriting to adm0 (to begin conversion for anin) rewriting to adm0 (to begin conversion for anim) adif0 has been set, but conversion for anim has not been completed. anin anin anim anim anin anin anim anim remarks 1. n = 0 to 5 2. m = 0 to 5 (9) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani5 input circuit. if your application is designed to be changed to backup power, the av dd pin must be supplied with the same voltage level as the v dd pin, as shown in figure 11-12. figure 11-12. av dd pin handling main power supply backup capacitor v dd av dd v ss av ss (10) av dd pin input impedance a series resistor string of several ten of k ? is connected between the av dd and av ss pins. consequently, if the output impedance of the reference voltage supply is high, the reference voltage supply will form a parallel connection with the series resistor string, cr eating a large referenc e voltage differential.
user?s manual u15075ej2v1ud 214 chapter 12 serial interface 20 12.1 serial interface 20 functions serial interface 20 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (2) asynchronous serial interface (uart) mode this mode is used to send and receive the one byte of data that follows a start bit. it supports full-duplex communication. serial interface 20 contains an uart-dedicated baud rate generator, enabling communication over a wide range of baud rates. it is also possible to define baud ra tes by dividing the frequency of the clock input to the asck20 pin. (3) 3-wire serial i/o mode (swit chable between msb-first a nd lsb-first transmission) this mode is used to transmit 8-bit data, using three lines: a serial clock (sck20) line and two serial data lines (si20 and so20). as it supports simultaneous transmissi on and reception, 3-wire serial i/o mode requires less processing time for data transmission than asynchr onous serial interface mode. because, in 3-wire serial i/o mode, it is possible to select whether 8-bit dat a transmission begins with the msb or lsb, serial interface 20 can be connected to any device regardless of whether that device is designed for msb-first or lsb-first transmission. 3-wire serial i/o mode is useful for connecting peri pheral i/o circuits and display controllers having conventional synchronous serial interfaces, such as those of the 75xl, 78k, and 17k series devices. 12.2 serial interface 20 configuration serial interface 20 includes the following hardware. table 12-1. configuration of serial interface 20 item configuration registers transmission shi ft register 20 (txs20) reception shift register 20 (rxs20) reception buffer register 20 (rxb20) control registers serial operati on mode register 20 (csim20) asynchronous serial interfac e mode register 20 (asim20) asynchronous serial interface st atus register 20 (asis20) baud rate generator control register 20 (brgc20) port mode register 2 (pm2) port 2 (p2)
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 215 internal bus reception buffer register 20 (rxb20) switching of the first bit asynchronous serial interface status register 20 (asis20) serial operation mode register 20 (csim20) reception shift register 20 (rxs20) csie20 sse20 dap20 dir20 csck20 ckp20 pe20 fe20 ove20 txe20 rxe20 ps201 ps200 cl20 sl20 asynchronous serial interface mode register 20 (asim20) transmission shift register 20 (txs20) transmission shift clock selector csie20 dap20 data phase control reception shift clock si20/p25/ rxd20 so20/p24/ txd20 4 parity detection stop bit detection reception data counter parity operation stop bit addition transmission data counter sl20, cl20, ps200, ps201 reception enabled reception clock detection clock start bit detection csie20 csck20 sck20/p23/ asck20 ss20/p22 clock phase control reception detected internal clock output external clock input transmission and reception clock control baud rate generator note 4 tps203 tps202 tps201 tps200 csie20 csck20 f x /2 to f x /2 8 baud rate generator control register 20 (brgc20) intst20 intsr20/intcsi20 internal bus figure 12-1. block diagram of serial interface 20 note see figure 12-2 for the configuration of the baud rate generator. port mode register (pm24)
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 217 (1) transmission shift register 20 (txs20) txs20 is a register in which trans mission data is prepared. the transmi ssion data is output from txs20 bit- serially. when the data length is seven bits, bits 0 to 6 of t he data in txs20 will be transmissi on data. writing data to txs20 triggers transmission. txs20 can be written with an 8-bit memory m anipulation instruction, but cannot be read. reset input sets txs20 to ffh. caution do not write to txs20 during transmission. txs20 and reception buffer register 20 (rxb20) are mapped at the same address, such that any attempt to read from txs20 results in a value being read from rxb20. (2) reception shift register 20 (rxs20) rxs20 is a register in which serial data, received at the rxd 20 pin, is converted to parallel data. once one entire byte has been received, rxs20 feeds the reception data to recept ion buffer register 20 (rxb20). rxs20 cannot be manipulated di rectly by a program. (3) reception buffer register 20 (rxb20) rxb20 holds a reception data. a new reception data is transferred from reception shift register 20 (rxs20) every 1-byte data reception. when the data length is seven bits, the reception data is sent to bits 0 to 6 of rxb20, in which the msb is always fixed to 0. rxb20 can be read with an 8-bit memory manipul ation instruction, but cannot be written. reset input makes rxb20 undefined. caution rxb20 and transmission shift register 20 (txs20) are mapped at the same address, such that any attempt to write to rxb20 result s in a value being written to txs20. (4) transmission controller the transmission controller controls transmission. for ex ample, it adds start, parity, and stop bits to the data in transmission shift register 20 (txs20), according to the setting of asynchronous serial interface mode register 20 (asim20). (5) reception controller the reception controller controls re ception according to the setting of asynchronous serial interface mode register 20 (asim20). it also checks for errors, such as parity errors, during recepti on. if an error is detected, asynchronous serial interface status register 20 (asis20) is set accord ing to the status of the error.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 218 12.3 serial interface 20 control registers serial interface 20 is controlled by the following six registers. ? serial operation mode register 20 (csim20) ? asynchronous serial interfac e mode register 20 (asim20) ? asynchronous serial interface status register 20 (asis20) ? baud rate generator contro l register 20 (brgc20) ? port mode register 2 (pm2) ? port 2 (p2) (1) serial operation mode register 20 (csim20) csim20 is used to make the settings related to 3-wire serial i/o mode. csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim20 to 00h. figure 12-3. format of serial operation mode register 20 csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20 outputs at the rising edge of sck20 ss20 pin selection function of ss20/p22 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is low active, and sck20 is at high level in the idle state clock is high active, and sck20 is at low level in the idle state cautions 1. bits 4 and 5 must be set to 0. 2. csim20 must be cleared to 00h if uart mode is selected.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 219 (2) asynchronous serial interface mode register 20 (asim20) asim20 is used to make the settings relat ed to asynchronous serial interface mode. asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. figure 12-4. format of asynchronous serial interface mode register 20 txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 00 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stop transmit operation enable rxe20 0 1 receive operation control receive operation stop receive operation enable ps201 0 0 1 1 parity bit specification ps200 0 1 0 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity cl20 0 1 transmit data character length specification 7 bits 8 bits sl20 0 1 transmit data stop bit length 1 bit 2 bits cautions 1. bits 0 and 1 must be set to 0. 2. if 3-wire serial i/o mode is selected, asim20 must be set to 00h. 3. switch operating modes after halt ing the serial transmit/receive operation.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 220 table 12-2. serial interf ace 20 operating mode settings (1) operation stop mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm25 p25 pm24 p24 pm23 p23 first bit shift clock p25/si20/ rxd20 pin function p24/so20/ txd20 pin function p23/sck20/ asck20 pin function 0 0 0 note 1 note 1 note 1 note 1 note 1 note 1 ? ? p25 p24 p23 other than above setting prohibited (2) 3-wire serial i/o mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm25 p25 pm24 p24 pm23 p23 first bit shift clock p25/si20/ rxd20 pin function p24/so20/ txd20 pin function p23/sck20/ asck20 pin function 0 1 external clock sck20 input 1 0 1 0 1 msb internal clock sck20 output 0 1 external clock sck20 input 0 0 1 1 1 note 2 note 2 0 1 0 1 lsb internal clock si20 note 2 so20 (cmos output) sck20 output other than above setting prohibited (3) asynchronous serial interface mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm25 p25 pm24 p24 pm23 p23 first bit shift clock p25/si20/ rxd20 pin function p24/so20/ txd20 pin function p23/sck20/ asck20 pin function 1 external clock asck20 input 1 0 0 0 0 note 1 note 1 0 1 note 1 note 1 internal clock p22 txd20 (cmos output) p23 1 external clock asck20 input 0 1 0 0 0 1 note 1 note 1 note 1 note 1 internal clock p24 p23 1 external clock asck20 input 1 1 0 0 0 1 0 1 note 1 note 1 lsb internal clock rxd20 txd20 (cmos output) p23 other than above setting prohibited notes 1. these pins can be used for port functions. 2. when only transmission is used, this pin can be used as p25 (cmos i/o). remark : don?t care.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 221 (3) asynchronous serial interface status register 20 (asis20) asis20 indicates the type of a recepti on error, if it occurs while asynch ronous serial interface mode is set. asis20 is set with a 1-bit or 8-bit memory manipulation instruction. the contents of asis 20 are undefined in 3-wire serial i/o mode. reset input sets asis20 to 00h. figure 12-5. format of asynchronous se rial interface status register 20 pe20 0 1 parity error flag 00000 pe20 fe20 ove20 asis20 symbol address after reset r/w ff71h 00h r 76543<2><1><0> no parity error has occurred. a parity error has occurred (when the transmit parity and receive parity did not match). fe20 0 1 flaming error flag no framing error has occurred. a framing error has occurred (when stop bit is not detected). note 1 ove20 0 1 overrun error flag no overrun error has occurred. an overrun error has occurred. note 2 (when the next receive operation is completed before the data is read from reception buffer register 20) notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim 20), the stop bit detection at rec eption is performed with 1 bit. 2. be sure to read reception buffer register 20 (r xb20) when an overrun error occurs. if not, every time the data is received an overrun error will occur.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 222 (4) baud rate generator cont rol register 20 (brgc20) brgc20 is used to specify the serial clock for serial interface 20. brgc20 is set with an 8-bit memo ry manipulation instruction. reset input sets brgc20 to 00h. figure 12-6. format of baud rate generator control register 20 tps203 0 0 0 0 0 0 0 0 1 selection of source clock for baud rate generator tps203 tps202 tps201 tps200 0000 brgc20 symbol address after reset r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 external clock input to the asck20 pin note setting prohibited (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) other than above tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 ? note an external clock can be used only in uart mode. cautions 1. when writing to brgc00 during a communication operation, the output of the baud rate generator is disrupted and communicat ions cannot be perf ormed normally. be sure not to write to brgc00 during a communication operation. 2. be sure not to select n = 1 during operation at f x > 2.5 mhz in uart mode because the resulting baud rate exceeds the rated range. 3. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the se ttings of tps200 to tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 223 the transmit/receive clock for the baud rate to be generat ed is either a signal scal ed from the system clock, or a signal scaled from the clock input to the asck20 pin. (a) generation of uart transmit/receive cl ock for baud rate from system clock the transmit/receive clock is generated by scaling t he system clock. the baud rate of a clock generated from the system clock is estimated by using the following expression. [baud rate] = [bps] f x : main system clock oscillation frequency n: value determined by the settings of tps 200 to tps203 as shown in figure 12-6 (2 n 8) table 12-3. example of relationships between system clock and baud rate error (%) baud rate (bps) n brgc20 set value f x = 5.0 mhz f x = 4.9152 mhz 1,200 8 70h 2,400 7 60h 4,800 6 50h 9,600 5 40h 19,200 4 30h 38,400 3 20h 76,800 2 10h 1.73 0 caution do not select n = 1 during operation at f x > 2.5 mhz because the resu lting baud rate exceeds the rated range. f x 2 n + 1 8
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 224 (b) generation of uart transmit/r eceive clock for baud rate from ext ernal clock input from asck20 pin the transmit/receive clock is generat ed by scaling the clock input from the asck20 pin. the baud rate of a clock generated from the clo ck input to the asck20 pin is es timated by using the following expression. [baud rate] = [bps] f asck : frequency of clock input to the asck20 pin table 12-4. relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 (c) generation of serial clock in 3- wire serial i/o mode from system clock the serial clock is generated by di viding the system clock. the seri al clock frequency is estimated by using the following expression. brgc20 does not need to be set when an external serial clock is input to the sck20 pin. serial clock frequency = [hz] f x : system clock oscillation frequency n: value determined by the settings of t ps200 to tps203 as shown in figure 12-6 (1 n 8) f asck 16 f x 2 n+1
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 225 12.4 serial interface 20 operation serial interface 20 provides the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode 12.4.1 operation stop mode in operation stop mode, serial trans fer is not executed, thereby reduc ing the power cons umption. the p23/sck20/asck20, p24/so20/tx d20, and p25/si20/rxd20 pins can be used as normal i/o ports. (1) register setting operation stop mode is set by serial operation mode register 20 (csim20) and asynchronous serial interface mode register 20 (asim20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 operation control in 3-wire serial i/o mode operation disabled operation enabled csie20 sse20 0 0 dap20 dir20 csck20 ckp20 csim20 <7> 6 5 4 symbol address after reset r/w ff72h 00h r/w 3210 caution bits 4 and 5 must be set to 0.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 226 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 receive operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 caution bits 0 and 1 must be set to 0.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 227 12.4.2 asynchronous serial interface (uart) mode in this mode, the one-byte data following the start bit is transmitted/received, enabli ng full-duplex communication. this device incorporates uart-dedi cated baud rate generator that enables communications at the desired baud rate. in addition, the baud rate can also be defined by dividing the clock input to the asck20 pin. the uart-dedicated baud rate generator also can output t he 31.25 kbps baud rate that complies with the midi standard. (1) register setting uart mode is set by serial operat ion mode register 20 (csim20), a synchronous serial interface mode register 20 (asim20), asynchronous serial interface st atus register 20 (asis20) , baud rate generator control register 20 (brgc20), port mode r egister 2 (pm2), and port 2 (p2).
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 228 (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim20 to 00h. set csim20 to 00h when uart mode is selected. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20 outputs at the rising edge of sck20 ss20 pin selection function of ss20/p22 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is low active, and sck20 is high level in the idle state clock is high active, and sck20 is low level in the idle state caution bits 4 and 5 must be set to 0.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 229 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 cautions 1. bits 0 and 1 must be set to 0. 2. switch operating modes after halt ing the serial transmit/receive operation.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 230 (c) asynchronous serial interface status register 20 (asis20) asis20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asis20 to 00h. pe20 0 1 parity error flag no parity error has occurred a parity error has occurred (when the transmit parity and receive parity did not match) no framing error has occurred a framing error has occurred (when stop bit is not detected) note 1 no overrun error has occurred an overrun error has occurred note 2 (when the next receive operation is completed before data is read from reception buffer register 20) fe20 0 1 0 1 framing error flag overrun error flag ove20 0 0 0 0 0 pe20 fe20 ove20 asis20 76 54 symbol address after reset r/w ff71h 00h r 3 <2> <1> <0> notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asi m20), the stop bit detection at reception is performed with 1 bit. 2. be sure to read reception buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is received an overrun error will occur.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 231 (d) baud rate generator cont rol register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input sets brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 1 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 ? setting prohibited selection of source clock for baud rate generator external clock input to asck20 pin note other than above tps203 tps202 tps201 tps200 0 0 0 0 brgc20 76 54 symbol address after reset r/w ff73h 00h r/w 3210 note can only be used in the uart mode. cautions 1. when writing to brgc20 duri ng a communication operation, the output of the baud rate generator is disrupted a nd communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. be sure not to select n = 1 during operation at f x > 2.5 mhz because the resulting baud rate exceeds the rated range. 3. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the settings of tps200 to tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 232 the baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input to the asck20 pin. (i) generation of transmit/receive clo ck for baud rate from system clock the transmit/receive clock is generated by scaling the system clock. the baud rate of a clock generated from the system clock is estimat ed by using the following expression. [baud rate] = [bps] f x : main system clock oscillation frequency n: values determined by the settings of tps 200 to tps203 as shown in the above table (2 n 8) table 12-5. example of relationships between system clock and baud rate error (%) baud rate (bps) n brgc20 set value f x = 5.0 mhz f x = 4.9152 mhz 1,200 8 70h 2,400 7 60h 4,800 6 50h 9,600 5 40h 19,200 4 30h 38,400 3 20h 76,800 2 10h 1.73 0 caution do not select n = 1 during operation at f x > 2.5 mhz because the resu lting baud rate exceeds the rated range. f x 2 n + 1 8
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 233 (ii) generation of transmit/receive clock for ba ud rate from external clock input from asck20 pin the transmit/receive clock is generated by scaling the clock input from t he asck20 pin. the baud rate of a clock generated from the clock input to the asck20 pin is estimated by using the following expression. [baud rate] = [bps] f asck : frequency of clock input to asck20 pin table 12-6. relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 f asck 16
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 234 (2) communication operation (a) data format the transmit/receive data format is as shown in figur e 12-7. one data frame c onsists of a start bit, character bits, parity bit, and stop bit(s). the specification of character bit length in one data frame, parity select ion, and specificat ion of stop bit length is carried out with asynchronous seri al interface mode register 20 (asim20). figure 12-7. format of asynchronous serial interface transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame ? start bits ................... 1 bit ? character bits............ 7 bits/8 bits ? parity bits .................. ev en parity/odd parity/ 0 parity/no parity ? stop bits .................... 1 bit/2 bits when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (b it 7) is ignored, and in reception t he most significant bit (bit 7) is always ?0?. the serial transfer rate is selected by baud rate generator control register 20 (brgc20). if a serial data receive error occurs, the receive error contents can be determi ned by reading the status of asynchronous serial interfac e status register 20 (asis20).
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 235 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receivi ng side. with even parit y and odd parity, a one-bit (odd number) error can be detected. with 0 par ity and no parity, an erro r cannot be detected. (i) even parity ? at transmission the parity bit is determined so t hat the number of bits with a va lue of ?1? in the transmit data including the parity bit may be even. t he parity bit value should be as follows. the number of bits with a value of ?1 ? is an odd number in transmit data: 1 the number of bits with a value of ?1 ? is an even number in transmit data: 0 ? at reception the number of bits with a value of ?1? in the receive data including parity bit is counted, and if the number is odd, a parity error occurs. (ii) odd parity ? at transmission conversely to the even parity, t he parity bit is determined so that the number of bits with a value of ?1? in the transmit data including parity bit may be odd. the parity bit value should be as follows. the number of bits with a value of ?1 ? is an odd number in transmit data: 0 the number of bits with a value of ?1 ? is an even number in transmit data: 1 ? at reception the number of bits with a value of ?1? in the receive data including parity bit is counted, and if the number is even, a parity error occurs. (iii) 0 parity when transmitting, the parity bit is set to ?0? irrespective of the transmit data. at reception, a parity bit check is not perform ed. therefore, a parit y error does not occur, irrespective of whether the parity bit is set to ?0? or ?1?. (iv) no parity a parity bit is not added to the trans mit data. at reception, data is received assuming that there is no parity bit. since there is no parit y bit, a parity error does not occur.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 236 (c) transmission a transmit operation is started by writing transmit data to transmission shift register 20 (txs20). the start bit, parity bit, and stop bi t(s) are added automatically. when the transmit operation starts, the data in txs20 is shifted out, and when txs20 is empty, a transmission completion interr upt (intst20) is generated. figure 12-8. asynchronous serial interf ace transmission completion interrupt timing (a) stop bit length: 1 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 (b) stop bit length: 2 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 caution do not rewrite asynchronous serial in terface mode register 20 (asim20) during a transmit operation. if the asim20 regi ster is rewritten during transmission, subsequent transmission may not be able to be performed (the normal state is restored by reset input). it is possible to determine whether transm ission is in progress by software by using a transmission completion interrupt (intst20) or the interrupt request flag (stif20) set by intst20.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 237 (d) reception when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is set (1), a receive operation is enabled and sampling of t he rxd20 pin input is performed. rxd20 pin input sampling is performed using t he serial clock specified by brgc20. when the rxd20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling star t timing signal is output. if the rxd20 pin input sampled again as a resu lt of this start timing signal is lo w, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampli ng is performed. when character data, a parity bit, and one stop bit ar e detected after the start bit, re ception of one frame of data ends. when one frame of data has been receiv ed, the receive data in the shi ft register is transferred to reception buffer register 20 (rxb20), and a recept ion completion interrupt (intsr20) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb20, and intsr20 is generated. if the rxe20 bit is reset (0) during the receive operat ion, the receive operation is stopped immediately. in this case, the contents of rxb20 and asynchronous serial interface status register 20 (asis20) are not changed, and intsr 20 is not generated. figure 12-9. asynchronous serial inte rface reception completion interrupt timing stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 caution be sure to read recepti on buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will occu r when the next data is received, and the receive error state will continue indefinitely.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 238 (e) receive errors the following three errors may occur during a receiv e operation: a parity e rror, framing error, and overrun error. after data reception, an error flag is se t in asynchronous serial interface status register 20 (asis20). receive error caus es are shown in table 12-7. it is possible to determine what kind of error o ccurred during reception by reading the contents of asis20 in the reception error interrupt servicing (see figures 12-5 and 12-10 ). the contents of asis20 are reset (0 ) by reading reception buffer regist er 20 (rxb20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 12-7. receive error causes receive errors cause parity error transmission-time parity and reception data parity do not match framing error stop bit not detected overrun error reception of next data is completed bef ore data is read from reception buffer register figure 12-10. receive error timing (a) parity error occurrence stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 (b) framing error or overrun error occurrence stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 cautions 1. the contents of the asis20 regi ster are reset (0) by reading reception buffer register 20 (rxb20) or receiving the next data. to ascertain the error contents, read asis20 before reading rxb20. 2. be sure to read recepti on buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 239 (3) cautions rela ted to uart mode (a) when bit 7 (txe20) of asynchronous serial inte rface mode register 20 ( asim20) is cleared during transmission, be sure to set transmission shift regist er 20 (txs20) to ffh, then set txe20 to 1 before executing the next transmission. (b) when bit 6 (rxe20) of asynchronous serial inte rface mode register 20 ( asim20) is cleared during reception, reception buffer regist er 20 (rxb20) and the receive comple tion interrupt (intsr20) are as follows. parity rxd20 pin rxb20 intsr20 <3> <1> <2> when rxe20 is set to 0 at a time indicated by <1> , rxb20 holds the previous data and intsr20 is not generated. when rxe20 is set to 0 at a time indicated by <2> , rxb20 renews the data and intsr20 is not generated. when rxe20 is set to 0 at a time indicated by <3> , rxb20 renews the data and intsr20 is generated.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 240 12.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional clocked se rial interface, such as the 75xl series, 78k series, and 17k series. communication is performed using three lines: a serial clock (sck20), serial output (so20), and serial input (si20). (1) register setting 3-wire serial i/o mode settings are performed usi ng serial operation mode register 20 (csim20), asynchronous serial interface mode register 20 (asim 20), baud rate generator contro l register 20 (brgc20), port mode register 2 (pm2), and port 2 (p2).
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 241 (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim20 to 00h. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin note output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20 outputs at the rising edge of sck20 ss20 pin selection function of ss20/p22 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is low active, and sck20 is at high level in the idle state clock is high active, and sck20 is at low level in the idle state note when the external input clock is selected, se t port mode register 2 (pm2) to input mode. caution bits 4 and 5 must be set to 0.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 242 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim20 to 00h. when 3-wire serial i/o mode is selected, asim20 must be set to 00h. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error occurs). odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 transmit data character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 cautions 1. bits 0 and 1 must be set to 0. 2. switch operating modes after halt ing the serial transmit/receive operation.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 243 (c) baud rate generator cont rol register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input sets brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 tps202 0 0 0 0 1 1 1 1 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps201 0 0 1 1 0 0 1 1 tps200 0 1 0 1 0 1 0 1 n 1 2 3 4 5 6 7 8 setting prohibited selection of source clock for baud rate generator other than above tps203 tps202 tps201 tps200 0 0 0 0 brgc20 76 54 symbol address after reset r/w ff73h 00h r/w 3210 caution when writing to brgc20 during a comm unication operation, the baud rate generator output is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the se ttings of tps200 to tps203 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz. if the internal clock is used as the serial clock fo r 3-wire serial i/o mode, set bits tps200 to tps203 to set the frequency of the serial clock. to obtain the frequency to be set, use the following expression. when an external clock is used, setting brgc20 is not necessary. serial clock frequency = [hz] f x : main system clock oscillation frequency n: values determined by the settings of tps 200 to tps203 as shown in the above table (1 n 8) f x 2 n + 1
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 244 (2) communication operation in 3-wire serial i/o mode, data transmission/recept ion is performed in 8-bit units. data is transmitted/received bit by bit in syn chronization with the serial clock. transmission shift register (txs20/sio20) and recept ion shift register (rxs20) shift operations are performed in synchronization with the fall of the serial clock (sck20). then transmit data is held in the so20 latch and output from the so20 pin. also, receive data input to the si 20 pin is latched in the reception buffer register (rxb20/sio20) on the rise of sck20. at the end of an 8-bit transfer, the operation of txs20/ sio20 and rxs20 stops automatically, and the interrupt request signal (i ntcsi20) is generated. figure 12-11. 3-wire serial i/o mode timing (1/7) (i) master operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 note si20 sio20 write intcsi20 note the value of the last bit previously output is output.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 245 figure 12-11. 3-wire serial i/o mode timing (2/7) (ii) slave operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 note so20 sio20 write intcsi20 note the value of the last bit previously output is output. (iii) slave operation (when dap20 = 0, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 note 1 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 246 figure 12-11. 3-wire serial i/o mode timing (3/7) (iv) master operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20 (v) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first rising edge of sck20. ma ke sure that the master outputs the first bit before the first rising of sck20.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 247 figure 12-11. 3-wire serial i/o mode timing (4/7) (vi) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first rising edge of sck20. make sure that the master outputs the first bit before the first rising of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state. (vii) master operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 248 figure 12-11. 3-wire serial i/o mode timing (5/7) (viii) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first falling edge of sck20. ma ke sure that the master outputs the first bit before the first falling of sck20. (ix) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first falling edge of sck20. make sure that the master outputs the first bit before the first falling of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 249 figure 12-11. 3-wire serial i/o mode timing (6/7) (x) master operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 do7 note do6 do5 do4 do3 do2 do1 di7 di6 di5 di4 di3 di2 di1 sck20 so20 si20 sio20 write intcsi20 di0 do0 note the value of the last bit previously output is output. (xi) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 sck20 si20 so20 sio20 write intcsi20 do7 note do6 do5 do4 do3 do2 do1 do0 di0 note the value of the last bit previously output is output.
chapter 12 serial interface 20 user?s manual u15075ej2v1ud 250 figure 12-11. 3-wire serial i/o mode timing (7/7) (xii) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 note 1 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state. (3) transfer start serial transfer is started by setting transfer data to the transmission shift regist er (txs20/sio20) when the following two conditions are satisfied. ? bit 7 (csie20) of serial operati on mode register 20 (csim20) = 1 ? internal serial clock is stopped or sck 20 is high after 8-bit serial transfer. caution if csie20 is set to ?1? after data is written to txs20/ sio20, transfer does not start. termination of 8-bit transfer stops the serial transfe r automatically and generates the interrupt request signal (intcsi20).
user?s manual u15075ej2v1ud 251 chapter 13 lcd controller/driver 13.1 lcd controller/driver functions the functions of the lcd controller/driver of the pd789426, 789436, 789446, and 789456 subseries are as follows. (1) automatic output of segment and common signal s based on automatic display data memory read (2) two different display modes: 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) (3) four different frame frequencies, selectable in each display mode (4) operation with a subsystem clock table 13-1 lists the maximum number of pixels that can be displayed in each display mode. table 13-1. number of segment ou tputs and maximum number of pixels bias method time slots common signals used maximum number of segments maximum number of pixels 3 com0 to com2 15 (5 segments 3 commons) pd789426, 789436 subseries 4 com0 to com3 5 20 (5 segments 4 commons) 3 com0 to com2 45 (15 segments 3 commons) pd789446, 789456 subseries 1/3 4 com0 to com3 15 60 (15 segments 4 commons) 13.2 lcd controller/driver configuration the lcd controller/driver in cludes the following hardware. table 13-2. configuration of lcd controller/driver item configuration display outputs segment signals: 5 ( pd789426 and 789436 subseries) 15 ( pd789446 and 789456 subseries) common signals: 4 (com0 to com3) control registers lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) lcd voltage amplification control register 0 (lcdva0)
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 252 lcdc03 lcdc02 lcdc01 lcdc00 2 2 f lcd 2 6 f lcd 2 7 f lcd 2 8 f lcd 2 9 lcdon0 vaon0 v lc0 com0 com1 com2 com3 3210 3210 65 74 fa00h lcdon0 3210 3210 65 74 fa0eh lcdon0 s14 f x /2 5 f x /2 6 f x /2 7 f xt s0 f lcd 3210 3210 65 74 fa04h lcdon0 s4 lcdcl lips0 gain v lc2 caph capl v lc1 vaon0 3210 3210 65 74 fa05h lcdon0 s5 lcdm00 lcd clock control register 0 (lcdc0) lcd display mode register 0 (lcdm0) lcd clock selector clock generator for boosting selector prescaler booster circuit segment voltage controller common voltage controller common driver ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ....... ......... . . . . . . . . . . . . . . . . . . segment driver segment driver segment driver segment driver selector selector selector selector pd789446, 789456 subseries only display data memory internal bus lcd voltage boost control register 0 (lcdva0) timing controller ? figure 13-1. block diagram of lcd controller/driver
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 253 13.3 registers controlling lcd controller/driver lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) lcd voltage amplification control register 0 (lcdva0) (1) lcd display mode register 0 (lcdm0) lcdm0 specifies whether to enable disp lay operation. it also specifies the operation mode, lcd drive power supply, and display mode. lcdm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdm0 to 00h.
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 254 figure 13-2. format of lcd display mode register 0 lcdon0 vaon0 0 lips0 0 0 0 lcdm00 lcdm0 symbol address after reset r/w ffb0h 00h r/w <7><6>5<4>3210 lcd controller/driver display mode selection lcdm00 0 1 4 3 lcd display enable/disable lcdon0 0 1 display off display on segment pin/common pin output control bit note lips0 0 1 lcd controller/driver operation mode note vaon0 0 1 no internal voltage amplification (normal operation) internal voltage amplification enabled (low-voltage operation) output ground level to segment/common pin output deselect level to segment pin and lcd waveform to common pin number of time slices bias mode 1/3 1/3 note when the lcd display panel is not used, the vaon0 and lips0 must be set to 0 to reduce power consumption. cautions 1. bits 1 to 3 and 5 must be set to 0. 2. when operating vaon0, follo w the procedure described below. a. to stop voltage amplification after switching display status from on to off : 1) set to display off st atus by setting lcdon0 = 0. 2) disable outputs of all the segment bu ffers and common buffers by setting lips0 = 0. 3) stop voltage amplification by setting vaon0= 0. b. to stop voltage amplification during display on status : setting prohibited. be sure to stop vo ltage amplification afte r setting display off. c. to set display on from voltage amplification stop status : 1) start voltage amplification by setti ng vaon0 = 1, then wait for about 500 ms. 2) set all the segment buffers and comm on buffers to non-display output status by setting lips0 = 1. 3) set display on by setting lcdon0 = 1.
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 255 (2) lcd clock control register 0 (lcdc0) lcdc0 specifies the lcd source clock and lcd clock. the frame frequency is determined according to the lcd clock and number of time slices. lcdc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdc0 to 00h. figure 13-3. format of lcd clock control register 0 lcdc03 lcdc02 lcdc01 lcdc00 lcdc0 symbol address after reset r/w ffb2h 00h r/w 76543210 lcd source clock (f lcd ) selection note lcdc03 0 0 1 1 lcdc02 0 1 0 1 lcd clock (lcdcl) selection lcdc01 0 0 1 1 lcdc00 0 1 0 1 0000 f lcd /2 6 f lcd /2 7 f lcd /2 8 f lcd /2 9 f xt (32.768 khz) f x /2 5 (156.3 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) note specify an lcd source clock (f lcd ) frequency of at least 32 khz. cautions 1. bits 4 to 7 must be set to 0. 2. before changing the lcdc0 setting, be sure to stop voltage amplification (vaon0 = 0). 3. set the frame frequency to 128 hz or lower. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. as an example, table 13-3 lists the frame frequencies used when f xt (32.768 khz) is supplied as the lcd source clock (f lcd ). table 13-3. frame frequencies (hz) lcd clock (f lcd ) display duty ratio f xt /2 9 (64 hz) f xt /2 8 (128 hz) f xt /2 7 (256 hz) f xt /2 6 (512 hz) 1/3 21 43 85 171 note 1/4 16 32 64 128 note this setting is prohibited because it c auses the frame frequency to exceed 128 hz.
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 256 (3) lcd voltage amplification control register 0 (lcdva0) lcdva0 controls the voltage amplification level during t he voltage amplifier operation. lcdva0 is set with a 1-bit or 8-bi t memory manipulation instruction. reset input sets lcdva0 to 00h. figure 13-4. format of lcd voltage amplification control register 0 0 gain lcdva0 symbol address after reset r/w ffb3h 00h r/w 7654321<0> gain 0 1 1.5 times (specification of the lcd panel used is 4.5 v.) 1.0 times (specification of the lcd panel used is 3 v.) 0 0 0 0 00 reference voltage (v lc2 ) level selection note note select the settings according to the specif ications of the lcd panel that is used. caution before changing the lcdva0 setting, be su re to stop voltage amplification (vaon0 = 0). remark the typ. value is indicat ed as the reference voltage (v lc2 ) value.
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 257 13.4 setting lcd controller/driver set the lcd controller/driver using the following procedure. <1> set the frame frequency using lcd cl ock control register 0 (lcdc0). <2> set the voltage amplification level using lcd vo ltage amplification contro l register 0 (lcdva0). gain = 0: v lc0 = 4.5 v, v lc1 = 3 v, v lc2 = 1. 5 v gain = 1: v lc0 = 3 v, v lc1 = 2 v, v lc2 = 1 v <3> set the time division using lcdm00 (bit 0 of lcd display mode register 0 (lcdm0)). <4> enable voltage amplification by setting vao n0 (bit 6 of lcdm0) (vaon0 = 1). <5> wait for 500 ms or more after setting vaon0. <6> set lips0 (bit 4 of lcdm0) (lips0 = 1) and output the deselect potential. <7> start output corresponding to each data memory by setting lcdon0 (bit 7 of lcdm0) (lcdon0 =1). 13.5 lcd display data memory the lcd display data memory is mapped at addresses fa00h to fa0eh. data in the lcd display data memory can be displayed on the lcd panel us ing the lcd controller/driver. figure 13-5 shows the relationship between the c ontents of the lcd disp lay data memory and the segment/common outputs. that part of the display data memory which is not used for display can be used as ordinary ram. figure 13-5. relationship between lcd display data memory cont ents and segment/common outputs ( pd789446, 789456 subseries) s14 fa0eh s13 fa0dh s12 fa0ch s11 s2 fa02h s1 fa01h s0 fa00h com3 com2 com1 com0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address caution no memory has been installe d as the higher 4 bits of the lcd di splay data memory. be sure to set 0 to them.
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 258 13.6 common and segment signals each pixel of the lcd panel turns on when the pot ential difference between the corresponding common and segment signals becomes a specif ic voltage (lcd drive voltage, v lcd ) or higher. it turns off when the potential difference becomes lower than v lcd . applying dc voltage to the common and segment signals for an lcd panel would deteriorate it. to avoid this problem, this lcd panel is driven with ac voltage. (1) common signals each common signal is selected sequentially according to a specified number of time slots at the timing listed in table 13-4. in the static di splay mode, the same signal is output to com0 to com3 in common. in the three-time slot m ode, keep the com3 pin open. table 13-4. com signals com signal number of time slots com0 com1 com2 com3 three-time slot mode open four-time slot mode (2) segment signals the segment signals correspond to lcd display data memory . bits 0, 1, 2, and 3 of each byte are read in synchronization with com0, com1, com2, and com3, respecti vely. if the contents of each bit are 1, it is converted to the select volt age, and if 0, it is conver ted to the deselect voltage. the conversion results are output to the segment pins. check, with the information given above, what combination of the front-s urface electrodes (corresponding to the segment signals) and the rear-sur face electrodes (corresponding to the common signals) forms display patterns in the lcd display data memory, and write t he bit data that corresponds to the desired display pattern on a one-to-one basis. bit 3 of the lcd display data memory is not used for lcd di splay in the three-time slot mode. so this bit can be used for purposes other than display. lcd display data memory bits 4 to 7 are fixed to 0. (3) output waveforms of common and segment signals when both common and segment signals are at t he select voltage, a display-on voltage of v lcd is obtained. the other combinations of the signals correspond to the display-off voltage.
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 259 figure 13-6 shows the common signal waveforms, and figure 13-7 shows the vo ltages and phases of the common and segment signals. figure 13-6. common signal waveforms comn (three-time slot mode) t f = 3 t v lc0 v ss v lcd v lc1 v lc2 t f = 4 t comn (four-time slot mode) v lc0 v lcd v lc1 v lc2 v ss t: one lcd clock period t f : frame frequency figure 13-7. voltages and phases of common and segment signals select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 v lc1 v lc1 t: one lcd clock period
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 260 13.7 display modes 13.7.1 three-time sl ot display example figure 13-9 shows how the 5-digit lcd panel having the disp lay pattern shown in figure 13-8 is connected to the segment signals (s0 to s14) and the co mmon signals (com0 to com2) of the pd789446 or pd789456 subseries chip. this example displays data ?123.45? in the lcd panel . the contents of the disp lay data memory (addresses fa00h to fa0eh) correspond to this display. the following description focuses on numeral ?3.? ( .) displayed in the third digit. to display ?3.? in the lcd panel, it is necessary to apply the select or des elect voltage to the s6 to s8 pins acco rding to table 13-5 at the timing of the common signals com0 to com2. table 13-5. select and desel ect voltages (com0 to com2) segment common s6 s7 s8 com0 select select deselect com1 select select deselect com2 select select ? according to table 13-6, it is dete rmined that the display data memory loca tion (fa06h) that corresponds to s6 must contain x111. figure 13-10 shows examples of lcd drive waveforms between the s6 signal and each common signal. when the select voltage is applied to s6 at the timing of com1 or com2, an alternate rectangle waveform, +v lcd /?v lcd , is generated to turn on the corresponding lcd segment. figure 13-8. three-time slot lcd disp lay pattern and electrode connections s 3n+2 s 3n com0 com2 s 3n+1 com1 remark n = 0 to 4
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 261 figure 13-9. example of connecting three-time slot lcd panel 001011011101110 001110011011011 00 10 11 00 10 bit 0 bit 1 bit 2 bit 3 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 com 3 com 2 com 1 com 0 open x? x? x? x? x? x?: can be used to store any data because ther e is no corresponding segment in the lcd panel. : can always be used to store any data becaus e of the three-time slot mode being used.
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 262 figure 13-10. three-time slot lcd drive waveform examples v lc0 v lc2 com0 +v lcd 0 com0-s6 ? v lcd v lc1 +1/3v lcd ? 1/3v lcd v ss0 v lc0 v lc2 com1 v lc1 v ss0 v lc0 v lc2 com2 v lc1 v ss0 v lc0 v lc2 s6 v lc1 v ss0 +v lcd 0 com1-s6 ? v lcd +1/3v lcd ? 1/3v lcd +v lcd 0 com2-s6 ? v lcd +1/3v lcd ? 1/3v lcd t f
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 263 13.7.2 four-time slot display example figure 13-12 shows how the 7-digit lcd panel having the di splay pattern shown in figure 13-11 is connected to the segment signals (s0 to s14) and the common signals (com0 to com3) of the pd789446 or pd789456 subseries chip. this example displays data ?123456.7? in the lcd panel. the contents of the display data memory (addresses fa00h to fa0eh) correspond to this display. the following description focuses on numeral ?6.? ( ) disp layed in the seventh digit. to display ?6.? in the lcd panel, it is necessary to apply the select or deselect volt age to the s2 and s3 pins according to table 13-6 at the timing of the common signals com0 to com3. table 13-6. select and desel ect voltages (com0 to com3) segment common s2 s3 com0 select select com1 deselect select com2 select select com3 select select according to table 13-7, it is dete rmined that the display data memory loca tion (fa02h) that corresponds to s2 must contain 1101. figure 13-13 shows examples of lcd drive waveforms between the s2 signal and the common signals. when the select voltage is applied to s2 at the timi ng of com0, an alternate rectangle waveform, +v lcd /?v lcd , is generated to turn on the corresponding lcd segment. figure 13-11. four-time slot lcd displ ay pattern and electrode connections remark n = 0 to 7 com0 s 2n com1 s 2n+1 com2 com3
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 264 figure 13-12. example of connecting four-time slot lcd panel 00010110111101 01111111101001 01100101011101 00101000101100 bit 0 bit 1 bit 2 bit 3 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 com 3 com 2 com 1 com 0
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 265 figure 13-13. four-time slot lcd drive wavef orm examples remark the waveforms of com2-s 2 and com3-s2 are omitted. t f v lc0 v lc2 com0 +v lcd 0 com0-s2 ? v lcd v lc1 +1/3v lcd ? 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v ss +v lcd 0 com1-s2 ? v lcd +1/3v lcd ? 1/3v lcd v lc0 v lc2 s2 v lc1 v ss
chapter 13 lcd controller/driver user?s manual u15075ej2v1ud 266 13.8 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 the pd789426, 789436, 789446, 789456 subseries c ontains a booster circuit ( 3 only) to generate a supply voltage to drive the lcd. the internal lcd reference voltage is output from the v lc2 pin. a voltage two times higher than that on v lc2 is output from the v lc1 pin and a voltage three ti mes higher than that on v lc2 is output from the v lc0 pin. the lcd reference voltage (v lc2 ) can be specified by setting lcd boos t control register 0 (lcdva0). the pd789426, 789436, 789446, 789456 subseries requires an external capacit or (recommended value: 0.47 f) because it employs a capacitance division met hod to generate a supply volt age to drive the lcd. table 13-7. output voltages of v lc0 to v lc2 pins lcdva0 gain = 0 gain = 1 lcd drive power supply pin v lc0 4.5 v 3.0 v v lc1 3.0 v 2.0 v v lc2 (lcd reference voltage) 1.5 v 1.0 v cautions 1. when using the lcd function, do not leave the v lc0 , v lc1 , and v lc2 pins open. refer to figure 13-14 for connection. 2. since the lcd dri ve voltage is separate from the main power supply, a constant voltage can be supplied regardless of v dd fluctuation. figure 13-14. example of conn ecting pins for lcd driver v lc0 v lc1 v lc2 c2 c3 c4 caph c1 external pin c1 = c2 = c3 = c4 = 0.47 f capl remark use a capacitor with as little leakage as possible. in addition, make c1 a nonpolar capacitor.
user?s manual u15075ej2v1ud 267 chapter 14 interrupt functions 14.1 interrupt function types the following two types of in terrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. a standby release signal is generated. one interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupt this interrupt undergoes mask control. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in table 14-1. a standby release signal is generated. 5 external and 9 internal interrupt source s are incorporated as maskable interrupts. 14.2 interrupt sources and configuration a total of 15 non-maskable and maskable interrupts are incorporated as interrupt sources (see table 14-1 ).
chapter 14 interrupt functions user?s manual u15075ej2v1ud 268 table 14-1. interrupt source list interrupt source interrupt type priority note 1 name trigger internal/ external vector table address basic configuration type note 2 non-maskable ? intwdt watchdog timer overflow (with watchdog timer mode 1 selected) (a) 0 intwdt watchdog timer overflow (with interval timer mode selected) internal 0004h (b) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 pin input edge detection external 000ch (c) intsr20 end of serial interface 20 uart reception 5 intcsi20 end of serial interface 20 3-wire sio transfer reception 000eh 6 intst20 end of serial interface 20 uart transmission 0012h 7 intwti interval timer interrupt 0014h 8 inttm90 generation of match signal of 16-bit timer 90 0016h 9 inttm50 generation of match signal of 8-bit timer 50 0018h 10 inttm60 generation of match signal of 8-bit timer 60 001ah 11 intad0 end of a/d conversion signal 001ch 12 intwt watch timer interrupt internal 001eh (b) maskable 13 intkr00 key return signal detection external 0020h (c) notes 1. priority is the priority order when several maskabl e interrupts are generated at t he same time. 0 is the highest order and 13 is the lowest order. 2. basic configuration types (a) to (c) correspond to (a) to (c) in figure 14-1. remark there are two interrupt sources for the wa tchdog timer (intwdt): non-maskable and maskable interrupts (internal). either one (but not both) should be selected for actual use.
chapter 14 interrupt functions user?s manual u15075ej2v1ud 269 figure 14-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt mk if ie internal bus intm0, intm1, krm00 interrupt request edge detector vector table address generator standby release signal intm0: external interrupt mode register 0 intm1: external interrupt mode register 1 krm00: key return mode register 00 if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag
chapter 14 interrupt functions user?s manual u15075ej2v1ud 270 14.3 registers controlling interrupt function the following five types of registers are used to control the interrupt functions. ? interrupt request flag registers 0, 1 (if0 and if1) ? interrupt mask flag registers 0, 1 (mk0 and mk1) ? external interrupt mode regi sters 0, 1 (intm0 and intm1) ? program status word (psw) ? key return mode register 00 (krm00) table 14-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. table 14-2. flags corresponding to interrupt request signal name interrupt request signal name interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intp3 intsr20/intcsi20 intst20 intwti inttm90 inttm50 inttm60 intad0 intwt intkr00 wdtif pif0 pif1 pif2 pif3 srif20 stif20 wtiif tmif90 tmif50 tmif60 adif0 wtif krif00 wdtmk pmk0 pmk1 pmk2 pmk3 srmk20 stmk20 wtimk tmmk90 tmmk50 tmmk60 admk0 wtmk krmk00
chapter 14 interrupt functions user?s manual u15075ej2v1ud 271 (1) interrupt request flag registers 0, 1 (if0 and if1) the interrupt request flag is set (1) when the correspondi ng interrupt request is generat ed or an instruction is executed. it is cleared (0) when an instruction is executed upon acknowledgement of an interrupt request or upon reset input. if0 and if1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input sets if0 and if1 to 00h. figure 14-2. format of interrupt request flag registers cautions 1. bit 7 of if1 and bit 6 of if0 must be set to 0. 2. the wdtif flag is r/w enabled only when a wa tchdog timer is used as an interval timer. if the watchdog timer mode 1 or 2 is used, set the wdtif flag to 0. 3. because port 3 has an alte rnate function as the external interrupt input, when the output level is changed by specifying th e output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. 0 1 0 krif00 wtif adif0 tmif60 tmif50 tmif90 wtiif if1 ffe1h 00h r/w interrupt request flag no interrupt request signal is generated interrupt request signal is generated; interrupt request state xxifx <6> <5> <4> <3> <2> <1> 7 <0> stif20 0 srif20 pif3 pif2 pif1 pif0 wdtif if0 r/w ffe0h 00h r/w symbol address after reset 6 <5> <4> <3> <2> <1> <7> <0>
chapter 14 interrupt functions user?s manual u15075ej2v1ud 272 (2) interrupt mask flag registers 0, 1 (mk0 and mk1) the interrupt mask flag is used to enable/disabl e the corresponding maskable interrupt service. mk0 and mk1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input sets mk0 and mk1 to ffh. figure 14-3. format of interrupt mask flag registers cautions 1. bits 7 of mk1 and bit 6 of mk0 must be set to 1. 2. if the wdtmk flag is read when the watc hdog timer is used in watc hdog timer mode 1 or 2, its value becomes undefined. 3. because port 3 has an alte rnate function as the external interrupt input, when the output level is changed by specifying th e output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. 0 1 1 krmk00 wtmk admk0 tmmk60 tmmk50 tmmk90 wtimk mk1 ffe5h ffh r/w interrupt servicing control interrupt servicing enabled interrupt servicing disabled <6> <5> <4> <3> <2> <1> 7 <0> xxmk stmk20 1 srmk20 pmk3 pmk2 pmk1 pmk0 wdtmk mk0 r/w ffe4h ffh r/w symbol address after reset 6 <5> <4> <3> <2> <1> <7> <0>
chapter 14 interrupt functions user?s manual u15075ej2v1ud 273 (3) external interrupt m ode register 0 (intm0) this register is used to specify a valid edge for intp0 to intp2. intm0 is set with an 8-bit memo ry manipulation instruction. reset input sets intm0 to 00h. figure 14-4. format of external interrupt mode register 0 0 0 1 1 es21 es20 es11 es10 es01 es00 0 0 intm0 r/w ffech 00h r/w 76543210 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 symbol address after reset intp0 valid edge selection falling edge rising edge setting prohibited both rising and falling edges intp1 valid edge selection falling edge rising edge setting prohibited both rising and falling edges intp2 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es00 es01 es11 es10 es20 es21 cautions 1. bits 0 and 1 must be set to 0. 2. before setting the intm0 register, be sure to set the relevant interr upt mask flag to 1 to disable interrupts. after that, clear (0) the interrupt request flag, then set the interrupt m ask flag to 0 to enable interrupts.
chapter 14 interrupt functions user?s manual u15075ej2v1ud 274 (4) external interrupt m ode register 1 (intm1) intm1 is used to specify a valid edge for intp3. intm1 is set with an 8-bit memo ry manipulation instruction. reset input sets intm1 to 00h. figure 14-5. format of external interrupt mode register 1 0 0 0 0 0 0 es31 es30 intm1 76543210 es31 0 0 1 1 intp3 valid edge selection es30 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges symbol address after reset r/w ffedh 00h r/w cautions 1. bits 2 to 7 must be set to 0. 2. before setting intm1, set pm k3 to 1 to disable interrupts. after that, clear (0) pif3, then set pmk3 to 0 to enable interrupts. (5) program status word (psw) the program status word is a regist er used to hold the instruction execut ion result and the current status for interrupt requests. the ie flag to set maskable interrupt enable/disable is mapped. besides 8-bit unit read/write, this register can carry out operations wit h a bit manipulation instruction and dedicated instructions (ei, di). w hen a vectored interrupt is acknowledged, the psw is automatically saved into a stack, and the ie flag is reset to 0. reset input sets psw to 02h. figure 14-6. configuration of program status word ie z 0 ac 0 0 1 cy psw 76543210 ie 0 1 02h symbol after reset used when normal instruction is executed interrupt acknowledgement enabled/disabled disabled enabled
chapter 14 interrupt functions user?s manual u15075ej2v1ud 275 (6) key return mode register 00 (krm00) this register sets the pin that detects a key return signal (falling edge of port 0). krm00 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets krm00 to 00h. figure 14-7. format of key return mode register 00 0 1 00 00000 krm000 krm00 fff5h 00h r/w address after reset r/w key return signal detection control no detection detection (detecting falling edge of port 0) 654321 70 krm000 symbol cautions 1. bits 1 to 7 must be set to 0. 2. before setting krm00, always set bit 6 of mk 1 (krmk00 = 1) to disable interrupts. after setting krm00, clear krmk00 after clearing bit 6 of if1 (krif00 = 0) to enable interrupts. 3. when p00 to p03 are in input mode, on-chip pull-up resistors are connected to p00 to p03 by the setting of krm000. after switching to output mode, the on-chip pull-up resistors are cut off. however, key return si gnal detection continues. 4. if any of the pins specifi ed for key return signal detection is low level, the key return signal cannot be detected even if a falling edge is generated at other key return pins. figure 14-8. block diagram of falling edge detector p00/kr0 p01/kr1 p02/kr2 p03/kr3 falling edge detector krmk00 krif00 set signal standby release signal key return mode register 00 (krm00) note selector note selector that selects t he pin used for falling edge input
chapter 14 interrupt functions user?s manual u15075ej2v1ud 276 14.4 interrupt servicing operation 14.4.1 non-maskable interrupt request acknowledgment operation the non-maskable interrupt request is unconditionally ack nowledged even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when the non-maskable interrupt request is acknowledged, psw and pc are saved to the stack in that order, the ie flag is reset to 0, the contents of the vector t able are loaded to the pc, and t hen program execution branches. figure 14-9 shows the flow from non-maskable interr upt request generation to acknowledgement, figure 14-10 shows the timing of non-maskable interrupt ackno wledgement, and figure 14-11 shows the acknowledgement operation when a number of non-ma skable interrupts are generated. caution during non-maskable interrupt service progr am execution, do not input another non-maskable interrupt request; if it is input, the servi ce program will be interr upted and the new non- maskable interrupt requ est will be acknowledged.
chapter 14 interrupt functions user?s manual u15075ej2v1ud 277 figure 14-9. flow from gene ration of non-maskable interrupt request to acknowledgment start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt servicing starts wdtm3 = 0 (non-maskable interrupt is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 14-10. timing of non-maskable interrupt request acknowledgment instruction instruction saving psw and pc, and jump to interrupt servicing interrupt servicing program cpu processing wdtif figure 14-11. non-maskable inte rrupt request acknowledgment second interrupt servicing first interrupt servicing nmi request (second) nmi request (first) main routine
chapter 14 interrupt functions user?s manual u15075ej2v1ud 278 14.4.2 maskable interrupt re quest acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vector ed interrupt is acknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the interrupt servicing afte r a maskable interrupt request has been generated is shown in table 14-3. refer to figures 14-13 and 14-14 for the ti ming of interrupt request acknowledgement. table 14-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an inte rrupt request is generat ed immediately before bt or bf instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generat ed at the same time, they are acknowledged starting from the one assigned the highest priority by the priority specification flag. a pending interrupt is acknowledged when the st atus where it can be acknowledged is set. figure 14-12 shows the algorithm of interrupt request acknowledgement. when a maskable interrupt request is a cknowledged, the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each in terrupt request is loaded to the pc, and execution branches. to return from interrupt servic ing, use the reti instruction. figure 14-12. interrupt request acknowledgment pr ogram algorithm start xxif = 1 ? xxmk = 0 ? ie = 1 ? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending xxif: interrupt request flag xxmk: interrupt mask flag ie: flag to control maskable interrupt reques t acknowledgement (1 = enable, 0 = disable) 1 f cpu
chapter 14 interrupt functions user?s manual u15075ej2v1ud 279 figure 14-13. interrupt request ackno wledgment timing (example: mov a, r) clock cpu mov a, r saving psw and pc, and jump to interrupt servicing 8 clocks interrupt servicing program interrupt if the interrupt request has generated an interrupt request flag (xxif) by t he time the instruction clocks under execution, n clocks (n = 4 to 10), are n ? 1, interrupt request acknowledgment processing will start following the completion of the instruction under exec ution. figure 14-13 shows an example us ing the 8-bit data transfer instruction mov a, r. because this instruction is executed in 4 clocks, if an interrupt request is generated bet ween the start of execution and the 3rd clock, interrupt request acknowledgment processing will ta ke place following the completion of mov a, r. figure 14-14. interrupt re quest acknowledgment timing (when interrupt request flag is gene rated in final clock under execution) clock cpu nop mov a, r saving psw and pc, and jump to interrupt servicing interrupt servicing program interrupt 8 clocks if the interrupt request flag (xxif) is generated in the final clock of the instruction, interrupt request acknowledgment processing will begin after executi on of the next instruction is complete. figure 14-14 shows an example whereby an interrupt request was generated in the 2nd clock of nop (a 2-clock instruction). in this case, the interr upt request will be processed after execution of mov a, r, which follows nop, is complete. caution when interrupt request flag registers 0 and 1 (if0 and if1), or interrupt mask flag registers 0 and 1 (mk0 and mk1) are being accessed, inte rrupt requests will be held pending. 14.4.3 multiple interrupt servicing multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced, can be serviced using the priority order. if multiple interr upts are generated at the same ti me, they are serviced in the order according to the priority assigned to each interrupt request in advance (refer to table 14-1 ).
chapter 14 interrupt functions user?s manual u15075ej2v1ud 280 figure 14-15. example of multiple interrupts example 1. acknowledging multiple interrupts intyy ei main servicing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 the interrupt request intyy is ackno wledged during the servicing of interrupt intxx and multiple interrupts are performed. before each interrupt reques t is acknowledged, the ei instruction is issued and the interrupt request is enabled. example 2. multiple interrupts are not performed because interrupts are disabled intyy ei main servicing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupt requests are disabled (the ei instruction has not been issued) in the interrupt intxx servicing, the interrupt request intyy is not a cknowledged and multiple interrupts are not performed. intyy is held pending and is acknowledged after intxx servicing is completed. ie = 0: interrupt requests disabled
chapter 14 interrupt functions user?s manual u15075ej2v1ud 281 14.4.4 putting interrupt requests on hold if an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being execut ed, the interrupt request will not be acknowledged until the instruct ion is completed. such instructions (interrupt request pendi ng instructions) are as follows. ? instructions that manipulate interrupt request flag registers 0, 1 (if0 and if1) ? instructions that manipulate interr upt mask flag registers 0, 1 (mk0 and mk1)
user?s manual u15075ej2v1ud 282 chapter 15 standby function 15.1 standby function and configuration 15.1.1 standby function the standby function is to reduce the power consumpti on of the system and can be e ffected in the following two modes: (1) halt mode this mode is set when the halt inst ruction is executed. the halt mode stops the operation clock of the cpu. the system clock oscillator continues oscillati ng. this mode does not r educe the power consumption as much as the stop mode, but is useful for resuming processing imm ediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is exec uted. the stop mode stops the main system clock oscillator and stops the entire system. the power consumpti on of the cpu can be s ubstantially reduced in this mode. the data memory can be reta ined at the low voltage (v dd = 1.8 v). therefore, this mode is useful for retaining the contents of t he data memory at an extremel y low power consumption. the stop mode can be released by an interrupt request, so that this mode can be used for intermittent operation. however, some time is required until the system clock oscilla tor stabilizes after the stop mode has been released. if processing must be resumed immedi ately by using an interrupt request, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memo ry before setting the standby mode are all retained. in addition, the status es of the output latch of the i/o ports and output buffer are also retained. caution to set the stop mode, be sure to stop th e operations of the periphe ral hardware, and then execute the stop instruction.
chapter 15 standby function user?s manual u15075ej2v1ud 283 15.1.2 register controlling standby function the wait time after the stop mode is released upon inte rrupt request until oscillation st abilizes is controlled with the oscillation stabilization time select register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, it takes 2 15 /f x , not 2 17 /f x , after reset input. caution when rc oscillation is selected, the oscilla tion stabilization time cannot be selected using osts. in the case of rc oscillation, the oscilla tion stabilization time is fixed to 2 7 /f cc . figure 15-1. format of oscillation st abilization time select register osts2 0 0 1 00000 osts2 osts1 osts0 osts r/w fffah 04h r/w 76543210 osts1 0 1 0 2 12 /f x 2 15 /f x 2 17 /f x (819 s) (6.55 ms) (26.2 ms) osts0 0 0 0 setting prohibited symbol address after reset oscillation stabilization time selection other than above caution the wait time after the stop mode is released does not in clude the time from stop mode release to clock oscillation start (? a? in the figure below), regard less of whether stop mode is released by reset input or by interrupt generation. a stop mode release x1 pin voltage waveform remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 15 standby function user?s manual u15075ej2v1ud 284 15.2 standby function operation 15.2.1 halt mode (1) halt mode the halt mode is set by exec uting the halt instruction. the operation status in the halt mode is shown in the following table. table 15-1. halt mode operating status halt mode operation status while the main system clock is running halt mode operation status while the subsystem clock is running item while the subsystem clock is running while the subsystem clock is not running while the main system clock is running while the main system clock is not running main system clock oscillation enabled oscillation stopped cpu operation stopped port (output latch) remains in the state existing before the selection of halt mode. 16-bit timer operation enabled operation stopped tm50 operation enabled note 1 8-bit timer tm60 operation enabled operation enabled note 2 watch timer operation enabled operation enabled note 3 operation enabled operation enabled note 4 watchdog timer operation enabled operation stopped serial interface operation enabled operation st opped note 5 a/d converter operation stopped lcd controller/driver operation enabled operation enabled note 3 operation enabled operation enabled note 4 external interrupt operation enabled note 6 notes 1. operation is enabled only when input signal from time r 60 (timer 60 operation is enabled) is selected as the count clock. 2. operation is enabled when tmi60 is selected as the count clock. 3. operation is enabled while the ma in system clock is selected. 4. operation is enabled while the subsystem clock is selected. 5. operation is enabled only when ex ternal clock is selected. 6. maskable interrupt that is not masked
chapter 15 standby function user?s manual u15075ej2v1ud 285 (2) releasing halt mode the halt mode can be released by the following three types of sources: (a) releasing by unmasked interrupt request the halt mode is released by an unm asked interrupt request. in this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed. if the inte rrupt is disabled, the instruction at the next address is executed. figure 15-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operation mode operation mode clock oscillation remarks 1. the broken line indicates the case where the in terrupt request that has released the standby mode is acknowledged. 2. the wait time is as follows: ? when vectored interrupt proce ssing is performed: 9 to 10 clocks ? when vectored interrupt processi ng is not performed: 1 to 2 clocks (b) releasing by non-maskable interrupt request the halt mode is released regardl ess of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed.
chapter 15 standby function user?s manual u15075ej2v1ud 286 (c) releasing by reset input when the halt mode is released by the reset signal, execution branc hes to the reset vector address in the same manner as the ordinary reset oper ation, and program exec ution is started. figure 15-3. releasing halt mode by reset input halt instruction reset signal wait (2 15 /f x : 6.55 ms) reset period halt mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation remark f x : main system clock oscillation frequency table 15-2. operation after releasing halt mode releasing source mkxx ie operation 0 0 executes next address instruction 0 1 executes interrupt servicing maskable interrupt request 1 x retains halt mode non-maskable interrupt request ? x executes interrupt servicing reset input - ? - ? reset processing x: don?t care
chapter 15 standby function user?s manual u15075ej2v1ud 287 15.2.2 stop mode (1) setting and operation st atus of stop mode the stop mode is set by exec uting the stop instruction. caution because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. when the stop mode is set, therefore, the halt mode is set immediately after the stop instruction has been execu ted, the wait time set by the oscillation stabilization time select register (osts) el apses, and then an operation mode is set. the operation status in the stop m ode is shown in the following table. table 15-3. stop mode operating status stop mode operation status while the main system clock is running item while the subsystem clock is running while the subsystem clock is not running main system clock osc illation stopped cpu operation stopped port (output latch) remains in the state existing before the selection of stop mode. 16-bit timer operation stopped tm50 operation enabled note 1 8-bit timer tm60 operation enabled note 2 watch timer operation enabled note 3 operation stopped watchdog timer operation enabled operation stopped serial interface operation enabled note 4 a/d converter operation stopped lcd controller/driver operation enabled note 3 operation stopped external interrupt operation enabled note 5 notes 1. operation is enabled only when input signal from time r 60 (timer 60 operation is enabled) is selected as the count clock. 2. operation is enabled when tmi60 is selected as the count clock. 3. operation is enabled while the subsystem clock is selected. 4. operation is enabled only when ex ternal clock is selected. 5. maskable interrupt that is not masked
chapter 15 standby function user?s manual u15075ej2v1ud 288 (2) releasing stop mode the stop mode can be released by the following two types of sources: (a) releasing by unmasked interrupt request the stop mode can be released by an unmasked interrupt request. in this case, if the interrupt is enabled to be acknowledged, vectored interrupt pr ocessing is performed, after the oscillation stabilization time has elapsed. if the interrupt is disabled, the in struction at the next address is executed. figure 15-4. releasing stop mode by interrupt stop instruction standby release signal wait (set time by osts) stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation remark the broken line indicates the case where the inte rrupt request that has re leased the standby mode is acknowledged.
chapter 15 standby function user?s manual u15075ej2v1ud 289 (b) releasing by reset input when the stop mode is released by the reset signal, the reset operation is performed after the oscillation stabilization time has elapsed. figure 15-5. releasing stop mode by reset input stop instruction reset signal wait stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation reset period remark f x : main system clock oscillation frequency table 15-4. operation after releasing stop mode releasing source mkxx ie operation 0 0 executes next address instruction 0 1 executes interrupt servicing maskable interrupt request 1 x retains stop mode reset input ? - ? - reset processing x: don?t care
user?s manual u15075ej2v1ud 290 chapter 16 reset function the following two operations are ava ilable to generate reset signals. (1) external reset input by reset pin (2) internal reset by watc hdog timer runaway time detection external and internal reset have no functional differences. in both cases, program exec ution starts at the address at 0000h and 0001h by reset input. when a low level is input to the r eset pin or the watchdog timer overflow s, a reset is applied and each hardware is set to the status shown in tabl e 16-1. each pin has a high impedance dur ing reset input or during oscillation stabilization time just after reset clear. when a high level is input to the r eset pin, the reset is cleared and progr am execution is started after the oscillation stabilization time has elapsed. the reset appli ed by the watchdog timer overfl ow is automatically cleared after reset, and program execution is started afte r the oscillation stabilization time has elapsed (see figures 16-2 to 16-4 .) cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pins become high impedance. figure 16-1. block diagram of reset function reset interrupt function count clock reset controller watchdog timer over- flow reset signal stop
chapter 16 reset function user?s manual u15075ej2v1ud 291 figure 16-2. reset timing by reset input x1 reset internal reset signal port pin during normal operation delay delay hi-z reset period (oscillation stops) normal operation (reset processing) oscillation stabilization time wait figure 16-3. reset timing by overflow in watchdog timer x1 overflow in watchdog timer internal reset signal port pin hi-z during normal operation reset period (oscillation continues) normal operation (reset processing) oscillation stabilization time wait figure 16-4. reset timing by reset input in stop mode x1 reset internal reset signal port pin delay delay hi-z stop instruction execution during normal operation reset period (oscillation stops) stop status (oscillation stops) normal operation (reset processing) oscillation stabilization time wait
chapter 16 reset function user?s manual u15075ej2v1ud 292 table 16-1. hardware status after reset (1/2) hardware status after reset program counter (pc) note 1 the contents of reset vector tables (0000h and 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose register undefined note 2 port (p0 to p3, p5, p7) (output latch) 00h port (p8, p9) (output latch) note 3 00h port mode register (pm0 to pm3, pm5, pm7) ffh port mode register (pm8, pm9) note 3 ffh pull-up resistor option register (pu0, pub2, pub3, pub7) 00h pull-up resistor option register (pub8 note 3 , pub9 note 3 ) 00h processor clock control register (pcc) 02h suboscillation mode register (sckm) 00h subclock control register (css) 00h oscillation stabilization time select register (osts) 04h timer counter (tm90) 0000h compare register (cr90) ffffh mode control register (tmc90) 00h capture register (tcp90) undefined 16-bit timer buzzer output control register (bzc90) 00h timer counter (tm50, tm60) 00h compare register (cr50, cr60, crh60) undefined mode control register (tmc50, tmc60) 00h 8-bit timer carrier generator output control register (tca60) 00h watch timer mode control register (wtm) 00h clock select register (wdcs) 00h watchdog timer mode register (wdtm) 00h serial operation mode register (csim20) 00h asynchronous serial interface mode register (asim20) 00h asynchronous serial interface st atus register (asis20) 00h baud rate generator control register (brgc20) 00h transmit shift register (txs20) ffh serial interface receive buffer register (rxb20) undefined a/d conversion result register (adcr0) 0000h mode register (adm0) 00h a/d converter analog input channel specificat ion register (ads0) 00h notes 1. during reset input and oscillation stabilization ti me wait, only the pc contents among the hardware statuses become undefined. all other hardware remains unchanged after reset. 2. the post-reset values are retained in the standby mode. 3. pd789426, 789436 subseries only
chapter 16 reset function user?s manual u15075ej2v1ud 293 table 16-1. hardware status after reset (2/2) hardware status after reset display mode register (lcdm0) 00h clock control register (lcdc0) 00h lcd controller/driver voltage amplification control register (lcdva0) 00h request flag register (if0, if1) 00h mask flag register (mk0, mk1) ffh external interrupt mode register (intm0, intm1) 00h interrupt key return mode register (krm00) 00h
user?s manual u15075ej2v1ud 294 chapter 17 pd78f9436, 78f9456 the pd78f9436 is a version with t he internal rom of the pd789426 and 789436 subseries replaced with flash memory and the pd78f9456 is a version with t he internal rom of the pd789446 and 789456 subseries replaced with flash memory. the differences between the pd78f9436, 78f9456 and the mask rom versions are shown in table 17-1. table 17-1. differences between pd78f9436, 78f9456 and mask rom versions flash memory version mask rom version part number item pd78f9436 pd78f9456 pd789425, 789435 pd789426, 789436 pd789445, 789455 pd789446, 789456 rom 12 kb 16 kb 12 kb 16 kb 12 kb 16 kb high-speed ram 512 bytes internal memory lcd display ram 5 4 bits 15 4 bits 5 4 bits 15 4 bits ic pin not provided provided v pp pin provided not provided electrical s pecifications refer to chapter 20 electrical specifications caution there are differences in noi se immunity and noise radiation be tween the flash memory and mask rom versions. when pre-producing an applicati on set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct suffici ent evaluations for the commercial samples (not engineering samples) of the mask rom version.
chapter 17 pd78f9436, 78f9456 user?s manual u15075ej2v1ud 295 17.1 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the pd78f9436 or 78f9456 mounted on the target system ( on-board). a flash memory program adapter (f a adapter), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. ? software can be modified after the microcontro ller is solder-mounted on the target system. ? distinguishing software facilities sm all-quantity, varied model production ? easy data adjustment when starting mass production 17.1.1 programming environment the following shows the environment required for pd78f9436 and 78f9456 flash memory programming. when flashpro iii (part no. fl-pr3, pg-fp3) or flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, a host machine is required to contro l the dedicated flash programme r. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals for flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 17-1. environment for wr iting program to flash memory host machine rs-232c usb dedicated flash programmer pd78f9436, 78f9456 v pp v dd v ss reset 3-wire serial i/o or uart
chapter 17 pd78f9436, 78f9456 user?s manual u15075ej2v1ud 296 17.1.2 communication mode use the communication mode shown in table 17-2 to perform communication between the dedicated flash programmer and pd78f9436 or 78f9456. table 17-2. communication mode list type setting note 1 cpu clock communication mode comm port sio clock in flashpro on target board multiple rate pins used number of v pp pulses 3-wire serial i/o sio ch-0 (3-wire, sync.) 100 hz to 1.25 mhz note 2 1, 2, 4, 5 mhz notes 2, 3 1 to 5 mhz note 2 1.0 si20/rxd20/p25 so20/txd20/p24 sck20/asck20/p23 0 uart uart ch-0 (async.) 4,800 to 76,800 bps notes 2, 4 5 mhz note 5 4.91 or 5 mhz note 2 1.0 rxd20/si20/p25 txd20/so20/p24 8 notes 1. selection items for type settings on the dedicated flash programmer (flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)). 2. the possible setting range differs depending on the voltage. for details, refer to chapter 20 electrical specifications . 3. 2 or 4 mhz only for flashpro iii 4. because signal wave slew also affects uart communication, in addition to the baud rate error, thoroughly evaluate the slew. 5. only for flashpro iv. however, when using flashpro iii, be sure to select the clock of the resonator on the board. uart cannot be used with the clock supplied by flashpro iii. figure 17-2. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n v pp pulses
chapter 17 pd78f9436, 78f9456 user?s manual u15075ej2v1ud 297 figure 17-3. example of connecti on with dedicated flash programmer (a) 3-wire serial i/o dedicated flash programmer vpp1 vdd reset sck so si clk note 1 gnd v pp v dd reset sck20 si20 so20 x1 v ss pd78f9436, 78f9456 (b) uart dedicated flash programmer vpp1 vdd reset so si clk notes 1, 2 gnd v pp v dd reset r x d20 t x d20 x1 v ss pd78f9436, 78f9456 notes 1. when supplying the system clock from a dedicated flash programme r, connect the clk and x1 pins and cut off the resonator on the board. when using the clock oscillated by the on-board resonator, do not connect the clk pin. 2. when using uart with flashpro iii, t he clock of the resonator connect ed to the x1 pin must be used, so do not connect the clk pin. caution the v dd pin, if already connected to the power suppl y, must be connected to the vdd pin of the dedicated flash programmer. when usi ng the power supply connected to the v dd pin, supply voltage before starting programming.
chapter 17 pd78f9436, 78f9456 user?s manual u15075ej2v1ud 298 if flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv ( part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, the following signals are generated for the pd78f9436 and 78f9456. for details, refer to the manual of flashpro iii/flashpro iv. table 17-3. pin connection list signal name i/o pin function pin name 3-wire serial i/o uart vpp1 output write voltage v pp vpp2 ? ? ? vdd i/o v dd voltage generation/ voltage monitoring v dd note note gnd ? ground v ss clk output clock output x1 reset output reset signal reset si input receive signal so20, txd20 so output transmit signal si20, rxd20 sck output transfer clock sck20 hs input handshake signal ? note v dd voltage must be supplied befor e programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected.
chapter 17 pd78f9436, 78f9456 user?s manual u15075ej2v1ud 299 17.1.3 on-board pin connections when programming on the target system, provide a connector on the target system to connect to the dedicated flash programmer. there may be cases in which an on-board function that switches from the normal operation mode to flash memory programming mode is required. input 0 v to the v pp pin in the normal operation m ode. a writing voltage of 10.0 v (typ.) is supplied to the v pp pin in the flash memory programmi ng mode. therefore, connect the v pp pin as follows. (1) connect a pull-down resistor of rv pp = 10 k ? to the v pp pin. (2) set the jumper on the board to switch the input of v pp pin to the programmer side or directly to gnd. the following shows an example of v pp pin connection. figure 17-4 v pp pin connection example pd78f9436, 78f9456 v pp pull-down resistor (rv pp ) connection pin of dedicated flash programmer the following shows the pins us ed by each serial interface. serial interface pins used 3-wire serial i/o si20, so20, sck20 uart rxd20, txd20 note that signal conflict or malfuncti on of other devices may occur when an on- board serial interface pin that is connected to another device is connected to the dedica ted flash programmer.
chapter 17 pd78f9436, 78f9456 user?s manual u15075ej2v1ud 300 (1) signal conflict a signal conflict occurs if the dedica ted flash programmer (output) is c onnected to a serial interface pin (input) connected to another dev ice (output). to prevent this signal conflict, isolate t he connection with the other device or put the other devic e in the output hi gh impedance status. figure 17-5. signal conflict (serial interface input pin) pd78f9436, 78f9456 signal conflict output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict. to prevent this, isolate the signal on the device side. connection pin of dedicated flash programmer other device input pin (2) malfunction of another device when the dedicated flash programmer (out put or input) is connected to a seri al interface pin (input or output) connected to another device (i nput), a signal may be output to the device, causing a malfunction. to prevent such malfunction, isolate the connecti on with other device or set so that the input signal to the device is ignored. figure 17-6. malfunction of another device pd78f9436, 78f9456 input pin input pin pin pin other device other device connection pin of dedicated flash programmer connection pin of dedicated flash programmer if the signal output by the pd78f9436 or 78f9456 affects another device in the flash memory programming mode, isolate the signal on the device side. if the signal output by the dedicated flash programmer affects another device, isolate the signal on the device side. pd78f9436, 78f9456
chapter 17 pd78f9436, 78f9456 user?s manual u15075ej2v1ud 301 when the reset signal of the dedicat ed flash programmer is connected to the reset signal connected to the reset signal generator on the board, a signal conflict occurs. to prevent this signal conflict, isolate the connection with the reset signal generator. if a reset signal is input from the user system in the flash memory programming mode, a normal programming operation will not be performed. do not input signals other than reset si gnals from the dedicated flash programmer during this period. figure 17-7. signal conflict (reset pin) reset pd78f9436, 78f9456 signal conflict output pin reset signal generator in the flash memory programming mode, the signal output by the reset signal generator and the signal output by the dedicated flash writer conflict, therefore, isolate the signal on the reset signal generator side connection pin of dedicated flash writer shifting to the flash memory programming mode sets all the pins except those used for flash memory programming communication to the st atus immediately after reset. therefore, if the exter nal device does not acknowledge an initial status such as t he output high impedance status, connect the external device to v dd or v ss via a resistor. when using an on-board clock, connection of x1, x2, xt1, and xt2 must conf orm to the methods in the normal operation mode. when using the clock output of the flash programmer, directly connect it to the x1 pin with the on-board oscillator disconnected, and leave the x2 pin open. the subsystem clock conf orms to the normal operation mode. to use the power output of the flash programmer, connect the v dd and v ss pins to v dd and gnd of the flash programmer, respectively. to use the on-board power supply, connec tion must conform to that in t he normal operation mode. however, because the voltage is monitored by t he flash programmer, therefore, v dd of the flash programmer must be connected. supply the same power as in the normal oper ation mode to the other power pins (av dd and av ss ). process the other pins (s0 to s14, com0 to com3, v lc0 to v lc2 , caph, and capl) in the same manner as in the normal operation mode.
chapter 17 pd78f9436, 78f9456 user?s manual u15075ej2v1ud 302 17.1.4 connection of adapter for flash writing the following figures show examples of the recommended connection when the adapter for flash writing is used. figure 17-8. wiring example for flash wr iting adapter using 3-wire serial i/o pd78f9436 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pd78f9456
chapter 17 pd78f9436, 78f9456 user?s manual u15075ej2v1ud 303 figure 17-9. wiring example for flash writing adapter using uart pd78f9436 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pd78f9456
user?s manual u15075ej2v1ud 304 chapter 18 mask options the mask rom versions of the pd789426, 789436, 789446, and 789456 subser ies have the following mask options. ? pull-up resistor the connection of on-chip pull-up resistors for port 5 (i/o port) can be switched in 1-bit units. <1> pull-up resistor is connected <2> pull-up resistor is not connected ? rc oscillation rc oscillation is selectable for the main system clock. <1> crystal/ceramic oscillation <2> rc oscillation caution the flash memory pr oducts do not have mask options.
user?s manual u15075ej2v1ud 305 chapter 19 instruction set this chapter lists the instruction set of the pd789426, 789436, 789446, and 789456 subserie s. for the details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) . 19.1 operation 19.1.1 operand identifier s and description methods operands are described in ?operand? colu mn of each instruction in accordanc e with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are described as they are. each symbol has the following meaning. ? #: immediate data specification ? $: relative address specification ? !: absolute address specification ? [ ]: indirect address specification in the case of immediate data, descr ibe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp, either functional names (x, a, c, etc.) or absolute names (names in parenthesis in the table below, r0, r1, r2, etc.) can be used for description. table 19-1. operand identifi ers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark see table 3-4 special function register list for symbols of special function registers.
chapter 19 instruction set user?s manual u15075ej2v1ud 306 19.1.2 description of ?operation? column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag indicating non-maskable interrupt servicing in progress ( ): memory contents indicated by addre ss or register contents in parenthesis x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) v: exclusive logical sum (exclusive or) ? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 19.1.3 description of ?flag? column (blank): unchanged 0: cleared to 0 1: set to 1 x: set/cleared according to the result r: previously saved value is restored
chapter 19 instruction set user?s manual u15075ej2v1ud 307 19.2 operation list mnemonic operands byte clock operation flag z ac cy mov r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 2 4 a r r, a note 1 2 4 r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte x x x a, psw 2 4 a psw psw, a 2 4 psw a x x x a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl+byte] 2 6 a (hl + byte) [hl+byte], a 2 6 (hl + byte) a xch a, x 1 4 a ? x a, r note 2 2 6 a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) a, [hl+byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set user?s manual u15075ej2v1ud 308 mnemonic operands byte clock operation flag z ac cy movw rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp rp, ax note 1 4 rp ax xchw ax, rp note 1 8 ax ? rp add a, #byte 2 4 a, cy a + byte x x x saddr, #byte 3 6 (saddr), cy (saddr) + byte x x x a, r 2 4 a, cy a + r x x x a, saddr 2 4 a, cy a + (saddr) x x x a, !addr16 3 8 a, cy a + (addr16) x x x a, [hl] 1 6 a, cy a + (hl) x x x a, [hl+byte] 2 6 a, cy a + (hl + byte) x x x addc a, #byte 2 4 a, cy a + byte + cy x x x saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy x x x a, r 2 4 a, cy a + r + cy x x x a, saddr 2 4 a, cy a + (saddr) + cy x x x a, !addr16 3 8 a, cy a + (addr16) + cy x x x a, [hl] 1 6 a, cy a + (hl) + cy x x x a, [hl+byte] 2 6 a, cy a + (hl + byte) + cy x x x sub a, #byte 2 4 a, cy a ? byte x x x saddr, #byte 3 6 (saddr), cy (saddr) ? byte x x x a, r 2 4 a, cy a ? r x x x a, saddr 2 4 a, cy a ? (saddr) x x x a, !addr16 3 8 a, cy a ? (addr16) x x x a, [hl] 1 6 a, cy a ? (hl) x x x a, [hl+byte] 2 6 a, cy a ? (hl + byte) x x x note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set user?s manual u15075ej2v1ud 309 mnemonic operands byte clock operation flag z ac cy subc a, #byte 2 4 a, cy a ? byte ? cy x x x saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy x x x a, r 2 4 a, cy a ? r ? cy x x x a, saddr 2 4 a, cy a ? (saddr) ? cy x x x a, !addr16 3 8 a, cy a ? (addr16) ? cy x x x a, [hl] 1 6 a, cy a ? (hl) ? cy x x x a, [hl+byte] 2 6 a, cy a ? (hl + byte) ? cy x x x and a, #byte 2 4 a a byte x saddr, #byte 3 6 (saddr) (saddr) byte x a, r 2 4 a a r x a, saddr 2 4 a a (saddr) x a, !addr16 3 8 a a (addr16) x a, [hl] 1 6 a a (hl) x a, [hl+byte] 2 6 a a (hl + byte) x or a, #byte 2 4 a a byte x saddr, #byte 3 6 (saddr) (saddr) byte x a, r 2 4 a a r x a, saddr 2 4 a a (saddr) x a, !addr16 3 8 a a (addr16) x a, [hl] 1 6 a a (hl) x a, [hl+byte] 2 6 a a (hl + byte) x xor a, #byte 2 4 a a v byte x saddr, #byte 3 6 (saddr) (saddr) v byte x a, r 2 4 a a v r x a, saddr 2 4 a a v (saddr) x a, !addr16 3 8 a a v (addr16) x a, [hl] 1 6 a a v (hl) x a, [hl+byte] 2 6 a a v (hl + byte) x remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set user?s manual u15075ej2v1ud 310 mnemonic operands byte clock operation flag z ac cy cmp a, #byte 2 4 a ? byte x x x saddr, #byte 3 6 (saddr) ? byte x x x a, r 2 4 a ? r x x x a, saddr 2 4 a ? (saddr) x x x a, !addr16 3 8 a ? (addr16) x x x a, [hl] 1 6 a ? (hl) x x x a, [hl+byte] 2 6 a ? (hl + byte) x x x addw ax, #word 3 6 ax, cy ax + word x x x subw ax, #word 3 6 ax, cy ax ? word x x x cmpw ax, #word 3 6 ax ? word x x x inc r 2 4 r r + 1 x x saddr 2 4 (saddr) (saddr) + 1 x x dec r 2 4 r r ? 1 x x saddr 2 4 (saddr) (saddr) ? 1 x x incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 x rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 x rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 x rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 x set1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1 x x x [hl].bit 2 10 (hl).bit 1 clr1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0 x x x [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 1 1 clr1 cy 1 2 cy 0 0 not1 cy 1 2 cy cy x remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set user?s manual u15075ej2v1ud 311 mnemonic operands byte clock operation flag z ac cy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 rrr push psw 1 2 (sp ? 1) psw, sp sp ? 1 rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 pop psw 1 4 psw (sp), sp sp + 1 rrr rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, ax 2 8 sp ax ax, sp 2 6 ax sp br !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 ax 1 6 pc h a, pc l x bc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 bt saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 bf saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 dbnz b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 19 instruction set user?s manual u15075ej2v1ud 312 19.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr !addr16 psw [de] [hl] [hl+byte] $addr1 6 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl+byte] mov note except r = a.
chapter 19 instruction set user?s manual u15075ej2v1ud 313 (2) 16-bit instructions movw, xchw, addw, subw, cmpw , push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1
chapter 19 instruction set user?s manual u15075ej2v1ud 314 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop
user?s manual u15075ej2v1ud 315 chapter 20 electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd av dd v dd = av dd ?0.3 to +6.5 v power supply voltage v pp pd78f9436, 78f9456 only, note 1 ?0.3 to +10.5 v v i1 p00 to p03, p10, p11, p20 to p26, p30 to p33, p60 to p65, p70 to p72, p80 note 2 , p81 note 2 , p90 to p97 note 2 , x1 (cl1), x2 (cl2), xt1, xt2, reset ?0.3 to v dd + 0.3 note 3 v n-ch open drain ?0.3 to +13 v input voltage v i2 p50 to p53 on-chip pull-up resistor ?0.3 to v dd + 0.3 note 3 v output voltage v o ?0.3 to v dd + 0.3 note 3 v per pin ?10 ma output current, high i oh total for all pins ?30 ma per pin 30 ma output current, low i ol total for all pins 160 ma during normal operation ?40 to +85 c operating ambient temperature t a during flash memory programming 10 to 40 c mask rom version ?65 to +150 c storage temperature t stg pd78f9436, 78f9456 ?40 to +125 c notes 1. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (1.8 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit va lue (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b 2. for pd789425, 789426, 789435, 789436, and 78f9436 3. 6.5 v or less
chapter 20 electrical specifications user?s manual u15075ej2v1ud 316 caution product quality may suffer if the absolute maximum rating is exce eded even momentarily for any parameter. that is, the absolute maximum ratings are rated value s at which the product is on the verge of suffering physical da mage, and therefore the product must be used under conditions that ensure that th e absolute maximum ra tings are not exceeded. remarks 1. unless otherwise specified, the characteristics of alternate-function pins ar e the same as those of port pins. 2. the items in parentheses apply when rc oscillation is selected (mask option).
chapter 20 electrical specifications user?s manual u15075ej2v1ud 317 main system clock osc illator characteristics ceramic/cr ystal oscillation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 1.0 5.0 mhz ceramic resonator x2 x1 v ss c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms oscillation frequency(f x ) note 1 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x2 x1 v ss c2 c1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 x2 x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 x2 open x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line thr ough which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the pr ogram before switching back to the main system clock. remark for the resonator selection and oscillator constan t, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 20 electrical specifications user?s manual u15075ej2v1ud 318 rc oscillation (mask option) (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f cc ) notes 1,2 v dd = oscillation voltage range 2.0 4.0 mhz v dd = 2.7 to 5.5 v 32 s rc resonator cl2 cl1 oscillation stabilization time note 3 v dd = 1.8 to 5.5 v 128 s cl1 input frequency (f cc ) note 1 1.0 4.0 mhz external clock cl1 cl2 open cl1 input high-/low- level width (t xh ,t xl ) 100 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. variations in external resistance and external capacitance are not included. 3. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figur e to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the pr ogram before switching back to the main system clock. rc oscillation frequen cy characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit f cc1 v dd = 2.7 to 5.5 v 1.5 2.0 2.5 mhz f cc2 r = 11.0 k ? , c = 22 pf v dd = 1.8 to 5.5 v 0.5 2.0 2.5 mhz f cc3 v dd = 2.7 to 5.5 v 2.5 3.0 3.5 mhz f cc4 r = 6.8 k ? , c = 22 pf v dd = 1.8 to 5.5 v 0.75 3.0 3.5 mhz f cc5 v dd = 2.7 to 5.5 v 3.5 4.0 4.7 mhz oscillation frequency f cc6 r = 4.7 k ? , c = 22 pf v dd = 1.8 to 5.5 v 1.0 4.0 4.7 mhz remark the typ. value of the oscillation frequency falls with in a range of 2.0 to 4.0 mhz, so set rc to one of the above values.
chapter 20 electrical specifications user?s manual u15075ej2v1ud 319 subsystem clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 crystal resonator xt2 xt1 v ss c4 c3 r oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 xt2 xt1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsyst em clock oscillator, wire as follows in the area en closed by the broken lines in the above figur e to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line thr ough which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is mo re prone to malfuncti on due to noise than the main system clock oscillator. particular care is therefore required with the wir ing method when the subsystem clock is used. remark for the resonator selection and oscillator constan t, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 20 electrical specifications user?s manual u15075ej2v1ud 320 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit per pin 10 ma output current, low i ol all pins 80 ma per pin ?1 ma output current, high i oh all pins ?15 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 p10, p11, p60 to p65, p70 to p72, p80 note , p81 note , p90 to p97 note v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih2 p50 to p53 on-chip pull- up resistor v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p00 to p03, p20 to p26, p30 to p33 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1 (cl1), x2 (cl2), xt1, xt2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 p10, p11, p60 to p65, p70 to p72, p80 note , p81 note , p90 to p97 note v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p00 to p03, p20 to p26, p30 to p33 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1 (cl1), x2 (cl2), xt1, xt2 v dd = 1.8 to 5.5 v 0 0.1 v v dd = 4.5 to 5.5 v, i oh = ?1 ma v dd ? 1.0 v output voltage, high v oh v dd = 1.8 to 5.5 v, i oh = ?100 a v dd ? 0.5 v 4.5 v dd 5.5 v, i ol = 10 ma 1.0 v v ol1 p00 to p03, p10, p11, p20 to p26, p30 to p33, p60 to p65, p70 to p72, p80 note , p81 note , p90 to p97 note , x1 (cl1), x2 (cl2), xt1, xt2 1.8 v dd < 4.5 v, i ol = 400 a 0.5 v 4.5 v dd < 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol2 p50 to p53 1.8 v dd < 4.5 v, i ol = 1.6 ma 0.4 v note pd789425, 789426, 789435, 789436, and 78f9436 only remarks 1. unless otherwise specified, the characteristics of alternate-function pins ar e the same as those of port pins. 2. the items in parentheses apply when rc oscillation is selected (mask option).
chapter 20 electrical specifications user?s manual u15075ej2v1ud 321 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit i lih1 p00 to p03, p10, p11, p20 to p26, p30 to p33, p60 to p65, p70 to p72, p80 note 1 , p81 note 1 , p90 to p97 note 1 , reset 3 a i lih2 v i = v dd x1 (cl1), x2 (cl2), xt1, xt2 20 a input leakage current, high i lih3 v i = 12 v p50 to p53 (n-ch open drain) 20 a i lil1 p00 to p03, p10, p11, p20 to p26, p30 to p33, p60 to p65, p70 to p72, p80 note 1 , p81 note 1 , p90 to p97 note 1 , reset ?3 a i lil2 x1 (cl1), x2 (cl2), xt1, xt2 ?20 a input leakage current, low i lil3 v i = 0 v p50 to p53 (n-ch open drain) ?3 note 2 a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ?3 a software pull-up resistor r 1 v i = 0 v p00 to p03, p10, p11, p20 to p26, p30 to p33, p70 to p72, p80 note 1 , p81 note 1 , p90 to p97 note 1 50 100 200 k ? mask option pull-up resistor note 3 r 2 v i = 0 v p50 to p53 10 30 60 k ? notes 1. pd789425, 789426, 789435, 789436, and 78f9436 only 2. if there is no on-chip pull-up resistor for p50 to p 53 (specified by the mask opt ion), if p50 to p53 have been set to input mode when a read instruction is ex ecuted to read from p50 to p53, a low-level input leakage current of up to ?30 a flows during only one cycle. at all other times, t he maximum leakage current is ?3 a. 3. mask rom products only remarks 1. unless otherwise specified, the characteristics of alternate-function pins ar e the same as those of port pins. 2. the items in parentheses apply when rc oscillation is selected (mask option).
chapter 20 electrical specifications user?s manual u15075ej2v1ud 322 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 1.8 2.9 ma v dd = 3.0 v 10% note 3 0.36 0.9 ma i dd1 5.0 mhz crystal oscillation operation mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.16 0.45 ma v dd = 5.0 v 10% note 2 0.96 1.92 ma v dd = 3.0 v 10% note 3 0.26 0.76 ma i dd2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.1 0.34 ma v dd = 5.0 v 10% 30 65 a v dd = 3.0 v 10% 9 30 a i dd3 32.768 khz crystal oscillation operation mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 4 14.5 a v dd = 5.0 v 10% 25 55 a v dd = 3.0 v 10% 7 25 a lcd not operating v dd = 2.0 v 10% 4 12.5 a v dd = 5.0 v 10% 28 64 a v dd = 3.0 v 10% 9.6 32.8 a i dd4 32.768 khz crystal oscillation halt mode note 4 lcd operating note 5 v dd = 2.0 v 10% 6 18.5 a v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5 a i dd5 stop mode note 6 v dd = 2.0 v 10% 0.05 3 a v dd = 5.0 v 10% note 2 2.7 4.7 ma v dd = 3.0 v 10% note 3 0.9 1.9 ma i dd6 5.0 mhz crystal oscillation a/d operating mode note 7 (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.6 1.25 ma v dd = 5.0 v 10% 1.65 3.0 ma v dd = 3.0 v 10% 0.65 1.44 ma i dd7 4.0 mhz rc oscillation operation mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% 0.38 1.05 ma v dd = 5.0 v 10% 1.1 2.29 ma v dd = 3.0 v 10% 0.6 1.28 ma i dd8 4.0 mhz rc oscillation halt mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% 0.35 0.82 ma v dd = 5.0 v 10% 2.4 4.8 ma v dd = 3.0 v 10% 1.1 2.44 ma power supply current note 1 (mask rom products) i dd9 4.0 mhz rc oscillation a/d operation mode note 7 (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% 0.71 1.85 ma notes 1. the port current (including the current that flow s to the on-chip pull-up resistor) is not included. 2. high-speed mode operation (when the processor clock control register (pcc) is set to 00h) 3. low-speed mode operation (when pcc is set to 02h) 4. when the main system clock is stopped 5. this is the current when the lcd controller/driver is operating (lcdon0 = 1, vaon0 = 1, lips0 = 1). the power supply current when the lcd is not oper ating (lcdon0 = 0, vaon0 = 1, lips0 = 0) is included in i dd2 (halt mode). 6. when the lcd voltage amplifier is st opped (lcdon0 = 0, vaon0 = 0) 7. this is the total current that flows to v dd and av dd . remark unless otherwise specified, the characteristics of al ternate-function pins are th e same as those of port pins.
chapter 20 electrical specifications user?s manual u15075ej2v1ud 323 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 4.5 9 ma v dd = 3.0 v 10% note 3 1 2 ma i dd1 5.0 mhz crystal oscillation operation mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.65 1.5 ma v dd = 5.0 v 10% note 2 1.4 2 ma v dd = 3.0 v 10% note 3 0.4 0.8 ma i dd2 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.19 0.42 ma v dd = 5.0 v 10% 100 230 a v dd = 3.0 v 10% 70 160 a i dd3 32.768 khz crystal oscillation operation mode note 4 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 58 120 a v dd = 5.0 v 10% 25 65 a v dd = 3.0 v 10% 7 29 a lcd not operating v dd = 2.0 v 10% 4 20 a v dd = 5.0 v 10% 28 70 a v dd = 3.0 v 10% 9.6 34 a i dd4 32.768 khz crystal oscillation halt mode note 4 lcd operating note 5 v dd = 2.0 v 10% 6 25 a v dd = 5.0 v 10% 0.1 17 a v dd = 3.0 v 10% 0.05 5.5 a i dd5 stop mode note 6 v dd = 2.0 v 10% 0.05 3.5 a v dd = 5.0 v 10% note 2 5.2 10.8 ma v dd = 3.0 v 10% note 3 1.4 3.8 ma power supply current note 1 ( pd78f9436, 78f9456) i dd6 5.0 mhz crystal oscillation a/d operating mode note 7 (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 1.0 2.9 ma notes 1. the port current (including the current that flow s to the on-chip pull-up resistor) is not included. 2. high-speed mode operation (when the processor clock control register (pcc) is set to 00h) 3. low-speed mode operation (when pcc is set to 02h) 4. when the main system clock is stopped 5. this is the current when the lcd controller/driver is operating (lcdon0 = 1, vaon0 = 1, lips0 = 1). the power supply current when the lcd is not oper ating (lcdon0 = 0, vaon0 = 1, lips0 = 0) is included in i dd2 (halt mode). 6. when the lcd voltage amplifier is stopped (lcdon0 = 0, vaon0 = 0) 7. this is the total current that flows to v dd and av dd . remark unless otherwise specified, the characteristics of al ternate-function pins are th e same as those of port pins.
chapter 20 electrical specifications user?s manual u15075ej2v1ud 324 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8.0 s operating with main system clock v dd = 1.8 to 5.5 v 1.6 8.0 s cycle time (minimum instruction execution time) t cy operating with subs ystem clock 114 122 125 s capture input high-/low- level width t cpth , t cptl cpt90 10 s v dd = 2.7 to 5.5 v 0 4 mhz tmi60 input frequency f tmi v dd = 1.8 to 5.5 v 0 275 khz v dd = 2.7 to 5.5 v 0.1 s tmi60 input high-/low- level width t timh , t timl v dd = 1.8 to 5.5 v 1.8 s interrupt input high- /low-level width t inth , t intl intp0 to intp3 10 s key return input low- level width t krl kr0 to kr3 10 s reset low-level width t rsl 10 s t cy vs. v dd (main system clock) power supply voltage v dd (v) cycle time t cy [ s] 123456 0.1 0.4 1.0 10 60 8.0 guaranteed operation range
chapter 20 electrical specifications user?s manual u15075ej2v1ud 325 (2) serial interface 20 (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2?50 ns sck20 high-/low-level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2?150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns delay time from sck20 to so20 output t so1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (b) 3-wire serial i/o mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low-level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns delay time from sck20 to so20 output t so2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (with ss20, to sck20 ) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (with ss20, from sck20 ) t kds2 v dd = 1.8 to 5.5 v 800 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps
chapter 20 electrical specifications user?s manual u15075ej2v1ud 326 (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s
chapter 20 electrical specifications user?s manual u15075ej2v1ud 327 ac timing measurement points (excl uding x1 (cl1) and xt1 inputs) 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd clock timing 1/f x t xl t xh x1 (cl1) input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih5 (min.) v il5 (max.) capture input timing cpt90 t cptl t cpth tmi timing 1/f ti t til t tih tmi60 interrupt input timing intp0 to intp3 t intl t inth key return input timing kr0 to kr3 t krl
chapter 20 electrical specifications user?s manual u15075ej2v1ud 328 reset input timing reset t rsl serial transfer timing 3-wire serial i/o mode: t kcym t klm t khm sck20 t sikm t ksim t ksom input data output data si20 so20 remark m = 1, 2 3-wire serial i/o mode (when using ss20): t kas2 so20 ss20 output data t kds2 uart mode (external clock input): t kcy3 t kl3 t kh3 asck20 t r t f
chapter 20 electrical specifications user?s manual u15075ej2v1ud 329 8-bit a/d converter characteristics ( pd789425, 789426, 789445, 789446) (t a = ?40 to +85 c, 1.8 v av dd = v dd 5.5 v, av ss = v ss =0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit av dd = 2.7 to 5.5 v 0.6 %fsr overall error note 1.2 %fsr av dd = 2.7 to 5.5 v 14 100 s conversion time t conv 28 100 s analog input voltage v ian 0 av dd v note excludes quantization error ( 0.2%) remark fsr: full scale range 10-bit a/d converter characteristics ( pd789435, 789436, 789455, 789456, 78f9436, 78f9456) (t a = ?40 to +85 c, 1.8 v av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.5 v av dd 5.5 v 0.2 0.4 %fsr 2.7 v av dd < 4.5 v 0.4 0.6 %fsr overall error note 1.8 v av dd < 2.7 v 0.8 1.2 %fsr 4.5 v av dd 5.5 v 14 100 s 2.7 v av dd < 4.5 v 19 100 s conversion time t conv 1.8 v av dd < 2.7 v 28 100 s 4.5 v av dd 5.5 v 0.4 %fsr 2.7 v av dd < 4.5 v 0.6 %fsr zero-scale error note ainl 1.8 v av dd < 2.7 v 1.2 %fsr 4.5 v av dd 5.5 v 0.4 %fsr 2.7 v av dd < 4.5 v 0.6 %fsr full-scale error note ainl 1.8 v av dd < 2.7 v 1.2 %fsr 4.5 v av dd 5.5 v 2.5 lsb 2.7 v av dd < 4.5 v 4.5 lsb non-integral linearity note inl 1.8 v av dd < 2.7 v 8.5 lsb 4.5 v av dd 5.5 v 1.5 lsb 2.7 v av dd < 4.5 v 2.0 lsb non-differential linearity note dnl 1.8 v av dd < 2.7 v 3.5 lsb analog input voltage v ian 0 av dd v note excludes quantization error ( 0.05%) remark fsr: full scale range
chapter 20 electrical specifications user?s manual u15075ej2v1ud 330 lcd characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit gain = 1 0.84 1.0 1.165 v lcd output voltage variation range v lcd2 c1 to c4 note 1 = 0.47 f gain = 0 1.26 1.5 1.74 v doubler output v lcd1 c1 to c4 note 1 = 0.47 f 2v lcd2 ?0.1 2.0v lcd2 2.0v lcd2 v tripler output v lcd0 c1 to c4 note 1 = 0.47 f 3v lcd2 ?0.15 3.0v lcd2 3.0v lcd2 v gain = 0 0.5 s 5.0 v dd 5.5 v 2.0 s 4.5 v dd < 5.0 v 1.0 s voltage amplification wait time note 2 t vawait gain = 1 1.8 v dd < 4.5 v 0.5 s lcd output voltage differential note 3 (common) v odc i o = 5 a 0 0.2 v lcd output voltage differential note 3 (segment) v ods i o = 1 a 0 0.2 v notes 1. this is a capacitor that is connected bet ween voltage pins used to drive the lcd. c1: a capacitor connected between caph and capl c2: a capacitor connected between v lc0 and v ss c3: a capacitor connected between v lc1 and v ss c4: a capacitor connected between v lc2 and v ss 2. this is the wait time from when voltage amplificat ion is started (vaon0 = 1) until display is enabled (lcdon0 = 0). 3. the voltage differential is the difference between the segment and common signal output?s actual and ideal output voltages. data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s
chapter 20 electrical specifications user?s manual u15075ej2v1ud 331 data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operation mode t srel t wait stop instruction execution v dddr reset data retention timing (standby re lease signal: stop mode release by interrupt request signal) v dd data retention mode stop mode halt mode operation mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request) oscillation stabilization wait time (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit crystal/ceramic oscillation 2 15 /f x s release by reset rc oscillation 2 7 /f cc s crystal/ceramic oscillation note 2 s oscillation stabilization wait time note 1 t wait release by interrupt rc oscillation 2 7 /f cc s notes 1. use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible with bits 0 to 2 (ost s0 to osts2) of the oscillation stabilization time selection register (osts). remarks 1. f x : main system clock oscillation frequency (crystal/ceramic oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation)
chapter 20 electrical specifications user?s manual u15075ej2v1ud 332 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1.0 5 mhz operating frequency f x v dd = 1.8 to 5.5 v 1.0 1.25 mhz write current note (v dd pin) i ddw when v pp supply voltage = v pp1 during f x = 5.0 mhz operation 7 ma write current note (v pp pin) i ppw when v pp supply voltage = v pp1 12 ma erase current note (v dd pin) i dde when v pp supply voltage = v pp1 during f x = 5.0 mhz operation 7 ma erase current note (v pp pin) i ppe when v pp supply voltage = v pp1 100 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s write count erase/write are regarded as 1 cycle 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the port current (including the current that flows to the on-chip pull-up resistors) is not included.
user?s manual u15075ej2v1ud 333 chapter 21 characteristic s curves of lcd controller/ driver (refre nce values) (1) characteristics curves of voltage amplification stabilization time the following shows the characteristics curves of the time from the start of voltage amplification (vaon0 = 1) and the changes in the lcd output voltage (when gain is set as 1 (using the 3 v display panel)). 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 lcd output voltage [v] v dd 4.5 v v dd 5 v v dd 5.5 v 0 500 1000 1500 2000 2500 3000 3500 4000 voltage amplification time [ms] v lcd0 v lcd1 v lcd2 lcd output voltage/voltage amplification time
chapter 21 characteristics curves of lcd controller/driver (refrence values) user?s manual u15075ej2v1ud 334 (2) temperature characteri stics of lcd output voltage the following shows the temperature charac teristics curves of lcd output voltage. lcd output voltage [v] v lcd2 v lcd1 v lcd0 v lcd2 v lcd1 v lcd0 ? 40 ? 30 ? 20 ? 100 1020304050607080 ? 40 ? 30 ? 20 ? 100 1020304050607080 temperature [?c] lcd output voltage/ temperature (when gain = 1) 5 4 3 2 1 0 5 4 3 2 1 0 lcd output voltage [v] temperature [?c] lcd output voltage/ temperature (when gain = 0)
user?s manual u15075ej2v1ud 335 chapter 22 package drawings 48 32 33 64 1 17 16 49 s s 64-pin plastic tqfp (12x12) item millimeters g 1.125 a 14.0 0.2 c 12.0 0.2 d f 1.125 14.0 0.2 b 12.0 0.2 n 0.10 p q 0.1 0.05 1.0 s r 3 + 4 ? 3 r h k j q g i s p detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. m h 0.32 + 0.06 ? 0.10 i 0.13 j k 1.0 0.2 0.65 (t.p.) l 0.5 m 0.17 + 0.03 ? 0.07 p64gk-65-9et-3 t u 0.6 0.15 0.25 f m a b cd n t l u 1.1 0.1
chapter 22 package drawings user?s manual u15075ej2v1ud 336 m 48 32 33 64 1 17 16 49 s n s j detail of lead end r k m i s l t p q g f h 64-pin plastic lqfp (10x10) item millimeters a b d g 12.0 0.2 10.0 0.2 1.25 12.0 0.2 h 0.22 0.05 c 10.0 0.2 f 1.25 i j k 0.08 0.5 (t.p.) 1.0 0.2 l 0.5 p 1.4 q 0.1 0.05 t 0.25 s 1.5 0.10 u 0.6 0.15 s64gb-50-8eu-2 r3 + 4 ? 3 n 0.08 m 0.17 + 0.03 ? 0.07 a b cd u note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition.
user?s manual u15075ej2v1ud 337 chapter 23 recommended soldering conditions the pd789426, 789436, 789446, and 789456 subseries should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) table 23-1. surface mounting ty pe soldering conditions (1/3) (1) pd789425gk- -9et: 64-pin plastic tqfp (12 12) pd789426gk- -9et: 64-pin plastic tqfp (12 12) pd789435gk- -9et: 64-pin plastic tqfp (12 12) pd789436gk- -9et: 64-pin plastic tqfp (12 12) pd789445gk- -9et: 64-pin plastic tqfp (12 12) pd789446gk- -9et: 64-pin plastic tqfp (12 12) pd789455gk- -9et: 64-pin plastic tqfp (12 12) pd789456gk- -9et: 64-pin plastic tqfp (12 12) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time:30 seconds max. (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-2 vps package peak temperature: 215 c, time:40 seconds max. (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vp15-107-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ws60-107-1 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry peak, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering me thods together (except for partial heating).
chapter 23 recommended soldering conditions user?s manual u15075ej2v1ud 338 table 23-1. surface mounting ty pe soldering conditions (2/3) (2) pd789425gb- -8eu: 64-pin plastic lqfp (10 10) pd789426gb- -8eu: 64-pin plastic lqfp (10 10) pd789435gb- -8eu: 64-pin plastic lqfp (10 10) pd789436gb- -8eu: 64-pin plastic lqfp (10 10) pd789445gb- -8eu: 64-pin plastic lqfp (10 10) pd789446gb- -8eu: 64-pin plastic lqfp (10 10) pd789455gb- -8eu: 64-pin plastic lqfp (10 10) pd789456gb- -8eu: 64-pin plastic lqfp (10 10) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time:30 seconds max. (at 210 c or higher), count: two times or less ir35-00-2 vps package peak temperature: 215 c, time:40 seconds max. (at 200 c or higher), count: two times or less vp15-00-2 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering me thods together (except for partial heating). (3) pd78f9436gk-9et: 64-pin plastic tqfp (12 12) pd78f9456gk-9et: 64-pin plastic tqfp (12 12) pd78f9436gb-8eu: 64-pin plastic lqfp (10 10) pd78f9456gb-8eu: 64-pin plastic lqfp (10 10) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time:30 seconds max. (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-2 vps package peak temperature: 215 c, time:40 seconds max. (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vp15-107-2 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry peak, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering me thods together (except for partial heating).
chapter 23 recommended soldering conditions user?s manual u15075ej2v1ud 339 table 23-1. surface mounting ty pe soldering conditions (3/3) (4) pd789425gk- -9et-a: 64-pin plastic tqfp (12 12) pd789426gk- -9et-a: 64-pin plastic tqfp (12 12) pd789435gk- -9et-a: 64-pin plastic tqfp (12 12) pd789436gk- -9et-a: 64-pin plastic tqfp (12 12) pd789445gk- -9et-a: 64-pin plastic tqfp (12 12) pd789446gk- -9et-a: 64-pin plastic tqfp (12 12) pd789455gk- -9et-a: 64-pin plastic tqfp (12 12) pd789456gk- -9et-a: 64-pin plastic tqfp (12 12) pd789425gb- -8eu-a: 64-pin plastic lqfp (10 10) pd789426gb- -8eu-a: 64-pin plastic lqfp (10 10) pd789435gb- -8eu-a: 64-pin plastic lqfp (10 10) pd789436gb- -8eu-a: 64-pin plastic lqfp (10 10) pd789445gb- -8eu-a: 64-pin plastic lqfp (10 10) pd789446gb- -8eu-a: 64-pin plastic lqfp (10 10) pd789455gb- -8eu-a: 64-pin plastic lqfp (10 10) pd789456gb- -8eu-a: 64-pin plastic lqfp (10 10) pd78f9436gk-9et-a: 64-pin plastic tqfp (12 12) pd78f9456gk-9et-a: 64-pin plastic tqfp (12 12) pd78f9436gb-8eu-a: 64-pin plastic lqfp (10 10) pd78f9456gb-8eu-a: 64-pin plastic lqfp (10 10) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 wave soldering when the pin pitch of the package is 0.65 mm or more, wave soldering can also be performed. for details, contact an nec elec tronics sales representative. ? partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering me thods together (except for partial heating).
user?s manual u15075ej2v1ud 340 appendix a development tools the following development tools are avail able for development of systems using the pd789426, 789436, 789446, and 789456 subseries. figure a-1 shows development tools. ? support to pc98-nx series unless specified otherwise, the pr oducts supported by ibm pc/at? co mpatibles can be used in pc98-nx series. when using the pc98-nx series, refer to the explanation of ibm pc/at compatibles. ? windows unless specified otherwise, ?windows? i ndicates the following operating systems. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt? ver.4.0
appendix a development tools user?s manual u15075ej2v1ud 341 figure a-1. development tools software package software package assembler package c compiler package device file c library source file note 1 integrated debugger system simulator project manager (windows version only) note 2 language processing software debugging software control software host machine (pc or ews) interface adapter flash memory writing tools flash programmer in-circuit emulator power supply unit emulation board emulation probe target system conversion socket or conversion adapter flash memory writing adapter flash memory notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assemb ler package and is available only for windows.
appendix a development tools user?s manual u15075ej2v1ud 342 a.1 software package various software tools for 78k/0s development are integrated in one package. the following tools are included. ra78k0s, cc78k0s, id78k0-ns, sm 78k0s, various device files sp78k0s software package part number: s sp78k0s remark in the part number differs dependi ng on the operating system used. s sp78k0s host machine os supply medium ab17 japanese windows cd-rom bb17 pc-9800 series, ibm pc/at and compatibles english windows note also operates under the dos environment a.2 language processing software program that converts program written in mnemonic into object codes that can be executed by a microcontroller. in addition, automatic functions to generate a symbol table and optimize branch instructions are also provided. used in combination with a device file (df789456) (sold separately). the assembler package is a do s-based application but may be us ed in the windows environment by using the project manager of windows (included in the package). ra78k0s assembler package part number: s ra78k0s program that converts program written in c language into object c odes that can be executed by a microcontroller. used in combination with an assembler package (ra78k0s) and device file (df789456) (both sold separately). the c compiler package is a do s-based application but may be us ed in the windows environment by using the project manager of window s (included in the assembler package). cc78k0s c compiler package part number: s cc78k0s file containing the informat ion inherent to the device. used in combination with other tools (ra78k 0s, cc78k0s, id78k0s-ns, sm78k0s) (all sold separately). df789456 note 1 device file part number: s df789456 source file of functions constituting the obj ect library included in the c compiler package. necessary for changing the object library included in the c compiler package according to the customer's specifications. since this is a source file , its working environment does not depend on any particular operating system. cc78k0s-l note 2 c library source file part number: s cc78k0s-l notes 1. df789456 is a common file that can be used with ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. 2. cc78k0s-l is not included in the software package (sp78k0s).
appendix a development tools user?s manual u15075ej2v1ud 343 remark in the part number differs depending on t he host machine and operating system used. s ra78k0s s cc78k0s host machine os supply media ab13 japanese windows 3.5" 2hd fd bb13 english windows ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows cd-rom 3p17 hp9000 series 700 tm hp-ux tm (rel.10.10) 3k17 sparcstation tm sunos tm (rel.4.1.4), solaris tm (rel.2.5.1) s df789456 s cc78k0s-l host machine os supply medium ab13 japanese windows 3.5" 2hd fd bb13 pc-9800 series, ibm pc/at and compatibles english windows 3p16 hp9000 series 700 hp-ux (rel.10.10) dat 3k13 3.5" 2hd fd 3k15 sparcstation sunos (rel.4.1.4), solaris (rel.2.5.1) 1/4" cgmt a.3 control software project manager control software provided for efficient user program development in the windows environment. the project manager allows a se ries of tasks required for user program development to be performed, including starti ng the editor, building, and starting the debugger. < caution > the project manager is included in the assembler package (ra78k0s). it cannot be used in an environment other than windows. a.4 flash memory writing tools flashpro iii (fl-pr3, pg-fp3) flashpro iv (fl-pr4, pg-fp4) flash writer flash programmer dedicated to microcont rollers incorporating flash memory. fa-64gk-9et fa-64gb-8eu flash memory writing adapter flash memory writing adapter. used in c onnection with flashpro iii or flashpro iv. fa-64gk-9et: 64-pin plas tic tqfp (gk-9et type) fa-64gb-8eu: 64-pin plas tic lqfp (gb-8eu type) remark fl-pr3, fl-pr4, fa-64gk-9et, and fa-64gb-8eu ar e products of naito densei machida mfg. co., ltd. for further information, contact: naito d ensei machida mfg. co., ltd. (+81-45-475-4191)
appendix a development tools user?s manual u15075ej2v1ud 344 a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and software of application system using the 78k/0s series. can be used with an in tegrated debugger (id78k0s-ns). used in combination with an ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-78k0s-ns-a in-circuit emulator in-circuit emulator with enhanced functions of the ie-78k0s-ns. the debug function is further enhanced by adding a coverage function and enhanc ing the tracer and timer functions. ie-70000-mc-ps-b ac adapter adapter for supplying power from a 100 to 240 vac outlet. ie-70000-98-if-c interface adapter adapter required when using a pc-9800 series (e xcept notebook type) as the host machine (c bus supported). ie-70000-cd-if-a pc card interface pc card and interface cable required when us ing a notebook type pc as the host machine (pcmica socket supported). ie-70000-pc-if-c interface adapter adapter required when using an ibm pc/at or compatible as the host machine (isa bus supported). ie-70000-pci-if-a interface adapter adapter required when using a personal comput er incorporating the pci bus as the host machine. ie-789456-ns-em1 emulation board emulation board for emulating the peripher al hardware inherent to the device. used in combination with an in-circuit emulator. np-64gk np-h64gk-tq emulation probe probe for connecting the in-circuit emulator and target system. used in combination with tgk-064sbw. tgk-064sbw conversion adapter conversion adapter used to connect a target system board designed to allow mounting a 64- pin plastic tqfp (gk-9et type) and the np-64gk/np-h64gk-tq. np-64gb-tq np-h64gb-tq emulation probe probe for connecting the in-circuit emulator and target system. used in combination with tgb-064sdp. tgb-064sdp conversion adapter conversion adapter used to connect a target system board designed to allow mounting a 64- pin plastic lqfp (gb-8eu type) and the np-64gb-tq/np-h64gb-tq. remarks 1. np-64gk, np-h64gk-tq, np-64gb- tq, and np-h64gb-tq are products of naito densei machida mfg. co., ltd. for further information, contact: naito densei machida mfg. co., ltd. (+81-45-475-4191) 2. tgk-064sbw and tgb-064sdp are products made by tokyo eletech corporation. for further information, c ontact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672)
appendix a development tools user?s manual u15075ej2v1ud 345 a.6 debugging tools (software) this debugger supports the in-cir cuit emulators ie-78k0s-ns and ie-78k0s-ns-a for the 78k/0s series. the id78k0s-n s is windows-based software. it has improved c-compatible debuggi ng functions and can display the results of tracing with the source program using an integrating window f unction that associates the source program, disassemble display, and memory display with the trace result. used in combination with a device file (df789456) (sold separately). id78k0s-ns integrated debugger part number: s id78k0s-ns this is a system simulator for the 78k/0s series. the sm78k0s is windows-based software. it can be used to debug the target system at c source level of assembler level while simulating the operation of the target system on the host machine. using sm78k0s, the logic and performance of the application can be verified independently of hardware development. therefore, the development efficiency can be enhanced and the software quality can be improved. used in combination with a device file (df789456) (sold separately). sm78k0s system simulator part number: s sm78k0s file containing the informat ion inherent to the device. used in combination with other tools (ra78k 0s, cc78k0s, id78k0s-ns, sm78k0s) (all sold separately). df789456 note device file part number: s df789456 note df789456 is a common file that can be used with ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. remark in the part number differs depending on the oper ating system used and the supply medium. s id78k0s-ns s sm78k0s host machine os supply medium ab13 japanese windows 3.5" 2hd fd bb13 english windows ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows cd-rom
user?s manual u15075ej2v1ud 346 appendix b notes on target system design the following shows the conditions when connecting the emulation probe to the c onversion adapter. follow the configuration below and consider t he shape of parts to be mounted on the target system when designing a system. among the products described in this appendix, np-64gb-tq, np-h64gb-t q, np-64gk, and np-h64gk-tq are products of naito densei machi da mfg. co., ltd, and tgb-064sdp and tgk-064sbw are products of tokyo eletech corporation. table b-1. distance between ie system and conversion adapter emulation probe conversion adapter distance between ie system and conversion adapter np-64gb-tq 170 mm np-h64gb-tq tgb-064sdp 370 mm np-64gk 170 mm np-h64gk-tq tgk-064sbw 370 mm figure b-1. distance between in-circu it emulator and conversion adapter (when 64gb is used) 170 mm note in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789456-ns-em1 conversion adapter: tgb-064sdp target system cn1 emulation probe np-64gb-tq np-h64gb-tq note distance when np-64gb-tq is used. when np -h64gb-tq is used, the distance is 370 mm.
appendix b notes on target system design user?s manual u15075ej2v1ud 347 figure b-2. connection conditions of targ et system (when np-64gb-tq is used) emulation probe np-64gb-tq emulation board ie-789456-ns-em1 22 mm 40 mm 34 mm target system conversion adapter tgb-064sdp 16 mm 16 mm 11 mm figure b-3. connection conditions of targ et system (when np-h64gb-tq is used) emulation probe np-h64gb-tq emulation board ie-789456-ns-em1 21.4 mm 42.6 mm 45 mm target system conversion adapter tgb-064sdp 16 mm 16 mm 11 mm
appendix b notes on target system design user?s manual u15075ej2v1ud 348 figure b-4. distance between in-circu it emulator and conversion adapter (when 64gk is used) 170 mm note in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789456-ns-em1 conversion adapter tgk-064sbw target system cn1 emulation probe np-64gk, np-h64gk-tq note distance when np-64gk is used. when np-h 64gk-tq is used, the distance is 370 mm. figure b-5. connection conditions of ta rget system (when np-64gk is used) emulation probe np-64gk emulation board ie-789456-ns-em1 21.95 mm 40 mm 34 mm target system conversion adapter tgk-064sbw 18.4 mm 11 mm 25 mm 18.4 mm
appendix b notes on target system design user?s manual u15075ej2v1ud 349 figure b-6. connection conditions of targ et system (when np-h64gk-tq is used) emulation probe np-h64gk-tq emulation board ie-789456-ns-em1 42 mm 45 mm 18.4 mm 11 mm target system conversion adapter tgk-064sbw 18.4 mm 21.95 mm 23 mm
user?s manual u15075ej2v1ud 350 appendix c register index c.1 register index (alphabetic order of register name) [a] analog input channel specific ation register 0 (a ds0)........................................................................... ........ 192, 205 a/d conversion result register 0 (adcr0 )....................................................................................... ............. 189, 202 a/d converter mode r egister 0 (adm0) ........................................................................................... ............. 191, 204 asynchronous serial interface mode register 20 (asi m20) .......................................................... 219, 226, 229, 242 asynchronous serial interface status register 20 (asi s20) ...................................................................... .... 221, 230 [b] baud rate generator control register 20 (brgc 20) .............................................................................. 2 22, 231, 243 buzzer output control register 90 (bzc 90) ...................................................................................... ..................... 125 [c] carrier generator output cont rol register 60 (t ca60) ........................................................................... ................ 148 [e] 8-bit compare regi ster 50 (cr50) ............................................................................................... .......................... 141 8-bit compare regi ster 60 (cr60) ............................................................................................... .......................... 141 8-bit compare regi ster h60 (crh 60)............................................................................................. ....................... 141 8-bit timer count er 50 (t m50).................................................................................................. ............................. 142 8-bit timer count er 60 (t m60).................................................................................................. ............................. 142 8-bit timer mode contro l register 50 (tmc 50)................................................................................... .................... 144 8-bit timer mode contro l register 60 (tmc 60)................................................................................... .................... 146 external interrupt mode register 0 (intm0) ..................................................................................... ..................... 273 external interrupt mode register 1 (intm1) ..................................................................................... ..................... 274 [ i ] interrupt mask flag regist ers 0, 1 (mk 0, mk1).................................................................................. .................... 272 interrupt request flag regi sters 0, 1 (if0, if1)............................................................................... ........................ 271 [k] key return mode r egister 00 (krm00)............................................................................................ ...................... 275 [l] lcd clock control r egister 0 (lcdc0) ........................................................................................... ....................... 255 lcd display mode r egister 0 (lcdm 0)............................................................................................ ..................... 253 lcd voltage amplification cont rol register 0 (lcd va0).......................................................................... .............. 256 [o] oscillation stabilization time select regist er (osts) .......................................................................... ................... 283 [p] port 0 (p0).................................................................................................................... .......................................... 80
appendix c register index user?s manual u15075ej2v1ud 351 port 1 (p1) .................................................................................................................... ......................................... 81 port 2 (p2) .................................................................................................................... ......................................... 82 port 3 (p3) .................................................................................................................... ......................................... 88 port 5 (p5) .................................................................................................................... ......................................... 90 port 6 (p6) .................................................................................................................... ......................................... 91 port 7 (p7) .................................................................................................................... ......................................... 92 port 8 (p8) .................................................................................................................... ......................................... 93 port 9 (p9) .................................................................................................................... ......................................... 94 port mode regist er 0 (p m0)..................................................................................................... ............................... 95 port mode regist er 1 (p m1)..................................................................................................... ............................... 95 port mode regist er 2 (p m2)..................................................................................................... ........................95, 126 port mode regist er 3 (p m3)..................................................................................................... ................95, 126, 149 port mode regist er 5 (p m5)..................................................................................................... ............................... 95 port mode regist er 7 (p m7)..................................................................................................... ............................... 95 port mode regist er 8 (p m8)..................................................................................................... ............................... 95 port mode regist er 9 (p m9)..................................................................................................... ............................... 95 processor clock cont rol regist er (pcc) ......................................................................................... ........................105 pull-up resistor option register 0 (pu0) ....................................................................................... ........................... 97 pull-up resistor option register b2 (pub2) ..................................................................................... ........................ 98 pull-up resistor option register b3 (pub3) ..................................................................................... ........................ 98 pull-up resistor option register b7 (pub7) ..................................................................................... ........................ 99 pull-up resistor option register b8 (pub8) ..................................................................................... ........................ 99 pull-up resistor option register b9 (pub9) ..................................................................................... .......................100 [r] receive buffer regi ster 20 (rxb20) ............................................................................................. .........................217 [s] serial operation mode r egister 20 (c sim20) .................................................................................218, 225, 228, 241 subclock control register (css)................................................................................................ ............................107 suboscillation mode r egister (sckm) ............................................................................................ .......................106 16-bit capture regi ster 90 (tcp90) ............................................................................................. ..........................122 16-bit compare regi ster 90 (cr90).............................................................................................. ..........................122 16-bit timer count er 90 (t m90) ................................................................................................. ............................122 16-bit timer mode contro l register 90 (tmc 90) .................................................................................. ...................123 [t] transmit shift regi ster 20 (txs20) ............................................................................................. ...........................217 [w] watch timer mode contro l register (wtm) ........................................................................................ ....................179 watchdog timer clock sele ct register (wdcs) .................................................................................... ..................184 watchdog timer mode r egister (wdtm) ............................................................................................ ...................185
appendix c register index user?s manual u15075ej2v1ud 352 c.2 register index (alphabeti c order of register symbol) [a] adcr0: a/d conversion re sult regi ster 0 ........................................................................................ .......... 189, 202 adm0: a/d converter mode regist er 0............................................................................................ ......... 191, 204 ads0: analog input channel s pecification r egister 0 ............................................................................ .. 192, 205 asim20: asynchronous serial interf ace mode register 20.......................................................... 219, 226, 229, 242 asis20: asynchronous serial in terface status register 20 ....................................................................... .. 221, 230 [b] brgc20: baud rate generator control regi ster 20 ............................................................................... 2 22, 231, 243 bzc90: buzzer output c ontrol regi ster 90....................................................................................... .................. 125 [c] cr50: 8-bit compar e regist er 50................................................................................................ ..................... 141 cr60: 8-bit compar e regist er 60................................................................................................ ..................... 141 cr90: 16-bit compar e regist er 90............................................................................................... .................... 122 crh60: 8-bit compar e register h60 .............................................................................................. .................... 141 csim20: serial operation mode register 20 ............................................................................... 218, 22 5, 228, 241 css: subclock c ontrol r egister ................................................................................................. .................... 107 [ i ] if0: interrupt reques t flag regi ster 0 ......................................................................................... .................. 271 if1: interrupt reques t flag regi ster 1 ......................................................................................... .................. 271 intm0: external interr upt mode regi ster 0 ...................................................................................... ................. 273 intm1: external interr upt mode regi ster 1 ...................................................................................... ................. 274 [k] krm00: key return mode regist er 00 ............................................................................................. ................... 275 [l] lcdc0: lcd clock cont rol regist er 0 ............................................................................................ .................... 255 lcdm0: lcd display mode regist er 0 ............................................................................................. .................. 253 lcdva0: lcd voltage amplificat ion control r egister 0 ........................................................................... ............. 256 [m] mk0: interrupt mask flag regist er 0............................................................................................ ................... 272 mk1: interrupt mask flag regist er 1............................................................................................ ................... 272 [o] osts: oscillation stabilizati on time select regi ster ........................................................................... .............. 283 [p] p0: port 0..................................................................................................................... ................................ 80 p1: port 1..................................................................................................................... ................................ 81 p2: port 2..................................................................................................................... ................................ 82 p3: port 3..................................................................................................................... ................................ 88
appendix c register index user?s manual u15075ej2v1ud 353 p5: port 5 ..................................................................................................................... ............................... 90 p6: port 6 ..................................................................................................................... ............................... 91 p7: port 7 ..................................................................................................................... ............................... 92 p8: port 8 ..................................................................................................................... ............................... 93 p9: port 9 ..................................................................................................................... ............................... 94 pcc: processor clo ck control regist er .......................................................................................... .................105 pm0: port mode register 0 ...................................................................................................... ....................... 95 pm1: port mode register 1 ...................................................................................................... ....................... 95 pm2: port mode register 2 ...................................................................................................... ................95, 126 pm3: port mode register 3 ...................................................................................................... ........95, 126, 149 pm5: port mode register 5 ...................................................................................................... ....................... 95 pm7: port mode register 7 ...................................................................................................... ....................... 95 pm8: port mode register 8 ...................................................................................................... ....................... 95 pm9: port mode register 9 ...................................................................................................... ....................... 95 pu0: pull-up resistor option regi ster 0 ........................................................................................ ................... 97 pub2: pull-up resistor option regi ster b2 ...................................................................................... ................... 98 pub3: pull-up resistor option regi ster b3 ...................................................................................... ................... 98 pub7: pull-up resistor option regi ster b7 ...................................................................................... ................... 99 pub8: pull-up resistor option regi ster b8 ...................................................................................... ................... 99 pub9: pull-up resistor option regi ster b9 ...................................................................................... ..................100 [r] rxb20: receive bu ffer regist er 20 .............................................................................................. ......................217 [s] sckm: suboscillati on mode r egister ............................................................................................. ...................106 [t] tca60: carrier generator out put control r egister 60 ............................................................................ .............148 tcp90: 16-bit capt ure regist er 90 .............................................................................................. .......................122 tm50: 8-bit time r counter 50 ................................................................................................... ........................142 tm60: 8-bit time r counter 60 ................................................................................................... ........................142 tm90: 16-bit time r counter 90 .................................................................................................. .......................122 tmc50: 8-bit timer mode control regi ster 50 .................................................................................... .................144 tmc60: 8-bit timer mode control regi ster 60 .................................................................................... .................146 tmc90: 16-bit timer mode control regi ster 90 ................................................................................... ................123 txs20: transmit sh ift regist er 20 .............................................................................................. .......................217 [w] wdcs: watchdog timer clo ck select regist er ..................................................................................... ..............184 wdtm: watchdog time r mode r egister ............................................................................................. ................185 wtm: watch timer m ode control regist er ......................................................................................... ..............179
user?s manual u15075ej2v1ud 354 appendix d revision history revisions up to this edition are shown below. the ?appli ed to? column indicates the chapter in each edition to which the revision was applied. (1/2) edition description applied to 2nd ? addition throughout of description of rc oscillation ? addition of 64-pin plastic lqfp (10 10) products to 1.3 ordering information chapter 1 general ? addition of 2.2.16 cl1, cl2 (in case of rc oscillation (mask option) only) chapter 2 pin functions ? total addition of description of rc oscillation ? addition of note to figure 5-3 format of suboscillation mode register chapter 5 clock generator ? modification of description of 6.4.1 operation as timer interrupt ? modification of figure 6-6 timing of timer interrupt operation ? modification of description of 6.4.2 operation as timer output ? modification of figure 6-8 timer output timing ? addition of 6.5.2 restrictions on rewriting 16-bit compare register 90 chapter 6 16-bit timer 90 ? modification of figure 7-4 format of 8-bit timer mode control register 50 ? modification of figure 7-5 format of 8-bit timer mode control register 60 ? addition of cautions to figure 7-6 format of carrier generator output control register 60 ? modification of table 7-3 interval time of timer 50 ? modification of table 7-4 interval time of timer 60 ? modification of table 7-5 square-wave output range of timer 50 (during f x = 5.0 mhz operation) ? modification of table 7-6 square-wave output range of timer 60 (during f x = 5.0 mhz operation) ? modification of table 7-7 interval time with 16-bit resolution (during f x = 5.0 mhz operation) ? modification of table 7-8 square-wave output range with 16-bit resolution (during f x = 5.0 mhz operation) ? addition of cautions to 7.4.3 operation as carrier generator chapter 7 8-bit timers 50, 60 ? addition of (c) generation of serial clock in 3-wire serial i/o mode from system clock to 12.3 (4) chapter 12 serial interface 20 ? addition of 13.8 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 chapter 13 lcd controller/driver ? addition of caution to 15.1.2 register controlling standby function chapter 15 standby function total revision of chapter chapter 17 pd78f9436, 78f9456 ? addition of description of rc oscillation chapter 18 mask options
appendix d revision history user?s manual u15075ej2v1ud 355 (2/2) edition description applied to 2nd addition of chapter chapter 20 electrical specifications chapter 21 characteristics curves of lcd controller/driver (reference values) chapter 22 package drawings chapter 23 recommended soldering conditions total revision of appendix appendix a development tools addition of appendix appendix b notes on target system design appendix d revision history deletion of appendix b embedded software ? addition of lead-free products chapter 1 general 2nd (modification version) addition of soldering conditi ons of lead-free products in table 23-1 surface mounting type soldering conditions chapter 23 recommended soldering conditions

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